Meihua Te Shen

US Patent:

6566270, May 20, 2003

Filed:

Sep 15, 2000

Appl. No.:

09/662677

Inventors:

Wei Liu - San Jose CA
Scott Williams - Sunnyvale CA
Stephen Yuen - Santa Clara CA
David Mui - San Jose CA
Meihua Shen - Fremont CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438706, 438714, 438719, 134 11, 134 12

Abstract:

A method for processing a substrate disposed in a substrate process chamber having a source power includes transferring the substrate into the substrate process chamber. A trench is etched on the substrate by exposing the substrate to a plasma formed from a first etchant gas by applying RF energy from the source power system and biasing the plasma toward the substrate. Byproducts adhering to inner surfaces of the substrate process chamber are removed by igniting a plasma formed from a second etchant gas including a halogen source in the substrate process chamber without applying bias power or applying minimal bias power. Thereafter, the substrate is removed from the chamber. At least 100 more substrates are processed with the etching-a-trench step and removing-etch-byproducts step before performing a dry clean or wet clean operation on the chamber.

US Patent:

6551941, Apr 22, 2003

Filed:

Feb 22, 2001

Appl. No.:

09/791446

Inventors:

Meihua Shen - Fremont CA
Oranna Yauw - Sunnyvale CA
Jeffrey D. Chinn - Foster City CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2100

US Classification:

438714, 216 67, 216 79, 438719, 438723, 438734, 438739, 438743

Abstract:

A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls. The remaining portion of the silicon-containing gate layer is etched at a lower bias power using a plasma generated from a second source gas which selectively etches the silicon-containing gate layer relative to the underlying gate dielectric layer, whereby a lower sidewall of the silicon-containing gate layer is formed and an upper surface of the gate dielectric layer is exposed. The etch stack is then exposed to a plasma generated from a third source gas which includes nitrogen, whereby a second, nitrogen-containing passivation layer is formed on the exposed sidewalls of the silicon-containing gate layer.

US Patent:

6599437, Jul 29, 2003

Filed:

Mar 20, 2001

Appl. No.:

09/813392

Inventors:

Oranna Yauw - Sunnyvale CA
Meihua Shen - Fremont CA
Nicolas Gani - Milpitas CA
Jeffrey D. Chinn - Foster City CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 213213

US Classification:

216 47, 216 49, 216 67, 216 72, 438695, 438696, 438710, 438714, 438725, 252 791

Abstract:

A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power. The first source gas and first substrate bias power provide a higher etch rate in dense feature areas than in isolated feature areas during the main etch step, whereas the second source gas and second substrate bias power provide a higher etch rate in isolated feature areas than in dense feature areas during the overetch step, resulting in an overall balancing effect.

US Patent:

6635573, Oct 21, 2003

Filed:

Oct 29, 2001

Appl. No.:

10/040109

Inventors:

Wilfred Pau - Santa Clara CA
Meihua Shen - Fremont CA
Jeffrey D. Chinn - Foster City CA

Assignee:

Applied Materials, Inc - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438689

Abstract:

We have discovered a method of detecting the approach of an endpoint during the etching of a material within a recess such as a trench or a contact via. The method provides a clear and distinct inflection endpoint signal, even for areas of a substrate containing isolated features. The method includes etching the material in the recess and using thin film interferometric endpoint detection to detect an endpoint of the etch process, where the interferometric incident light beam wavelength is tailored to the material being etched; the spot size of the substrate illuminated by the light beam is sufficient to provide adequate signal intensity from the material being etched; and the refractive index of the material being etched is sufficiently different from the refractive index of other materials contributing to reflected light from the substrate, that the combination of the light beam wavelength, the spot size, and the difference in refractive index provides a clear and distinct endpoint signal.

US Patent:

6784110, Aug 31, 2004

Filed:

Oct 1, 2002

Appl. No.:

10/263019

Inventors:

Jianping Wen - Cupertino CA 95014
Meihua Shen - Fremont CA 94539
Hung-Kwei Hu - Saratoga CA 95070

International Classification:

H01L 21302

US Classification:

438706, 438714, 438735

Abstract:

In a method of etching a substrate, a substrate is provided in a process zone, the substrate having a pattern of features comprising dielectric covering semiconductor. In a first stage, an energized first etching gas is provided in the process zone, the energized first etching gas having a first selectivity of etching dielectric to semiconductor of at least about 1. 8:1, wherein the dielectric is etched preferentially to the semiconductor to etch through the dielectric to at least partially expose the semiconductor. In a second stage, an energized second etching gas is provided in the process zone, the energized second etching gas having a second selectivity of etching dielectric to semiconductor of less than about 1:1. 8, wherein the semiconductor is etched preferentially to the dielectric.

US Patent:

6797188, Sep 28, 2004

Filed:

Feb 18, 2000

Appl. No.:

09/507629

Inventors:

Meihua Shen - Fremont CA 94539
Oranna Yauw - Sunnyvale CA 94087
Jeffrey Chinn - Foster City CA 94404

International Classification:

H01L 2100

US Classification:

216 46, 216 67, 216 79, 134 11, 134 21, 134 221, 438696, 438721, 438723, 438724, 438905

Abstract:

A method of etching a silicon-containing material in a substrate comprises placing the substrate in a process chamber and exposing the substrate to an energized gas comprising fluorine-containing gas, chlorine-containing gas and sidewall-passivation gas. The silicon-containing material on the substrate comprises regions having different compositions, and the volumetric flow ratio of the fluorine-containing gas, chlorine-containing gas, and sidewall-passivation gas is selected to etch the compositionally different regions at substantially similar etch rates.

US Patent:

6933243, Aug 23, 2005

Filed:

Oct 23, 2002

Appl. No.:

10/279320

Inventors:

Meihua Shen - Fremont CA, US
Yan Du - San Jose CA, US
Nicolas Gani - Milpitas CA, US
Oranna Yauw - Singapore, SG
Hakeem M. Oluseyi - Richmond CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L021/302

US Classification:

438720, 438722, 438734

Abstract:

Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

US Patent:

7064078, Jun 20, 2006

Filed:

Jan 30, 2004

Appl. No.:

10/768724

Inventors:

Wei Liu - San Jose CA, US
Jim Zhongyi He - Sunnyvale CA, US
Sang H. Ahn - Foster City CA, US
Meihua Shen - Fremont CA, US
Hichem M'Saad - Santa Clara CA, US
Wendy H. Yeh - Mountain View CA, US
Chistopher D. Bencher - San Jose CA, US

Assignee:

Applied Materials - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438717, 438723, 438724, 216 41, 216 58, 216 67, 216 72, 216 75, 216 79, 216 81

Abstract:

A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.