Matthew W King

Author:

Matthew King

ISBN #:

0787948659

Author:

Matthew A. King

ISBN #:

0662279514

Author:

Matthew J. King

ISBN #:

0080444288

US Patent:

6738070, May 18, 2004

Filed:

Jan 7, 2002

Appl. No.:

10/042083

Inventors:

Daniel Alan Brokenshire - Round Rock TX
David Arthur Dick - Austin TX
Matthew Edward King - Pflugerville TX
William B. Tiernan - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G09G 500

US Classification:

345587, 345588, 345586, 345581, 345582

Abstract:

A method and an apparatus for retrieving a mipmap from memory. The method and apparatus provide an efficient method of determining the location of the desired mipmap in memory by storing the address of each row of mipmaps and calculating the offset from the start of the row to the desired mipmap. The mipmap is retrieved from memory at the location corresponding to the sum of the start address and the offset.

US Patent:

6822486, Nov 23, 2004

Filed:

Aug 7, 2003

Appl. No.:

10/635968

Inventors:

Matthew E. King - Pflugerville TX
Peichun Liu - Austin TX
David Mui - Round Rock TX
Jieming Qi - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1700

US Classification:

327 99, 327407

Abstract:

In a first aspect, a method is provided for selecting a signal from a plurality of signals. The method includes the steps of (1) providing a plurality of multiplexers, each multiplexer configured to selectively output one of a plurality of signals input by the multiplexer using an output of the multiplexer; (2) selecting an input signal from one of the plurality of multiplexers to output; (3) outputting the selected input signal from the output of the one of the plurality of multiplexers; (4) forcing the outputs of the other of the plurality of multiplexers to a predetermined logic state; and (5) combining the outputs of the plurality of multiplexers so as to output the selected input signal. Numerous other aspects are provided.

US Patent:

7203811, Apr 10, 2007

Filed:

Jul 31, 2003

Appl. No.:

10/631542

Inventors:

Matthew Edward King - Pflugerville TX, US
David Mui - Round Rock TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G00F 13/28

US Classification:

711169, 710 22, 710 24, 710308

Abstract:

A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.

US Patent:

7444435, Oct 28, 2008

Filed:

Mar 14, 2007

Appl. No.:

11/686083

Inventors:

Matthew Edward King - Pflugerville TX, US
David Mui - Round Rock TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00
G06F 13/28
G06F 13/36

US Classification:

710 1, 710 22, 710 24, 710308

Abstract:

A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one processor has a local storage. The DMAC includes a DMA command queue (DMAQ) coupled to the local storage and configured to receive the list DMA command from the local storage and to enqueue the list DMA command. An issue logic is coupled to the DMAQ and configured to issue an issue request to the DMAQ. A request interface logic (RIL) is coupled to the DMAQ and configured to read the list DMA command based on the issue request. The RIL is further coupled to the local storage and configured to send a fetch request to the local storage to initiate a fetch of a list element of the list DMA command from the local storage to the DMAQ. Each list element comprises a stall bit indicating whether the list element is fenced and a DMA completion logic (DCL) is coupled to the at least one processor, the issue logic, and the RIL, and configured to indicate completion of all outstanding bus requests relating to the list element.

US Patent:

7512722, Mar 31, 2009

Filed:

Jul 31, 2003

Appl. No.:

10/631541

Inventors:

Matthew Edward King - Pflugerville TX, US
David Mui - Round Rock TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28
G06F 9/46

US Classification:

710 24, 710 22, 718104

Abstract:

A method, an apparatus, and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.

US Patent:

7644198, Jan 5, 2010

Filed:

Oct 7, 2005

Appl. No.:

11/246585

Inventors:

Matthew Edward King - Pflugerville TX, US
Peichun Peter Lui - Austin TX, US
David Mui - Round Rock TX, US
Jieming Qi - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28
G06F 3/00
G06F 13/00

US Classification:

710 22, 710 53, 711118

Abstract:

An improved DMAC translation mechanism is presented. DMA commands are “unrolled” based upon the transfer size of the DMA command and the amount of data that a computer system transfers at one time. For the first DMA request, a DMA queue requests a memory management unit to perform an address translation. The DMA queue receives a real page number from the MMU and, on subsequent rollout requests, the DMA queue provides the real page number to a bus interface unit without accessing the MMU until the transfer crosses into the next page. Rollout logic decrements the DMA command's transfer size after each DMA request, determines whether a new page has been reached, determines if the DMA command is completed, and sends write back information to the DMA queue for subsequent DMA requests.

US Patent:

7870309, Jan 11, 2011

Filed:

Dec 23, 2008

Appl. No.:

12/342501

Inventors:

Brian K. Flachs - Georgetown TX, US
Harm P. Hofstee - Austin TX, US
Charles R. Johns - Austin TX, US
Matthew E. King - Pflugerville TX, US
John S. Liberty - Round Rock TX, US
Brad W. Michael - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/14

US Classification:

710 22, 711215

Abstract:

A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

US Patent:

7877523, Jan 25, 2011

Filed:

Dec 10, 2008

Appl. No.:

12/331733

Inventors:

Matthew Edward King - Pflugerville TX, US
David Mui - Round Rock TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00
G06F 13/00

US Classification:

710 24, 710 22, 718104

Abstract:

An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.