Matthew B King

Author:

Matthew King

ISBN #:

0787948659

Author:

Matthew A. King

ISBN #:

0662279514

Author:

Matthew J. King

ISBN #:

0080444288

US Patent:

20080006536, Jan 10, 2008

Filed:

May 17, 2007

Appl. No.:

11/804261

Inventors:

Jerome Cuomo - Cary NC, US
Christopher Oldham - Raleigh NC, US
Matthew King - Raleigh NC, US

Assignee:

North Carolina State University - Raleigh NC

International Classification:

C12P 7/06
B03C 5/02
C13K 1/02
H05H 1/03
C08B 15/00

US Classification:

204672000, 127030000, 127034000, 127037000, 204157680, 204660000, 204671000, 435161000

Abstract:

Cellulosic material is treated by atmospheric-pressure (AP) plasma to enhance processes for extracting sugars from cellulosic material and fermenting sugars into alcohols or other chemicals. In one example, the AP plasma treatment is utilized to improve the release, activation or production of glucose and conversion of glucose to ethanol. The AP plasma treatment may be performed in conjunction with other processes such as depolymerization or degradation, for example hydrolysis, as well as fermentation. The AP plasma treatment may be performed as a substitute for pretreatment processes such as steam explosion, and in some implementations is sufficiently effective to serve as a substitute for hydrolytic processes or at least as an enhancement to hydrolytic processes or other depolymerization or degradation processes.

US Patent:

20220376104, Nov 24, 2022

Filed:

May 20, 2021

Appl. No.:

17/325488

Inventors:

- Durham NC, US
Kyle Bothe - Cary NC, US
Matthew King - Wake Forest NC, US

International Classification:

H01L 29/778
H01L 29/40
H01L 29/10
H01L 29/205
H01L 21/263

Abstract:

A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.