Matthew V Kaufmann

US Patent:

7449365, Nov 11, 2008

Filed:

Mar 14, 2006

Appl. No.:

11/375433

Inventors:

Arya Reza Behzad - Poway CA, US
Matthew Vernon Kaufmann - Morgan Hill CA, US
Malcolm MacIntosh - Escondido CA, US
Jacob Jude Rael - Lake Forest CA, US
Henry K. Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 21/00

US Classification:

438108, 438612, 257E21511

Abstract:

Forming a wafer level chip scale flip chip package includes determining isolation requirements of an integrated circuit formed in a semi conductive substrate from package signal connections of the wafer level chip scale flip chip package. Operation may further include, based upon the integrated circuit characteristics, selecting a thickness of at least one dielectric layer isolating a top metal layer of the integrated circuit from the package signal connections of the wafer level chip scale flip chip package, determining a minimum pitch of the package signal connections of the wafer level chip scale flip chip package, and determining a maximum lateral distance from the signal pad to a servicing package signal connection of the wafer level chip scale flip chip package and determining a position of the servicing package signal connection of the wafer level chip scale flip chip package based upon the maximum lateral distance.

US Patent:

7834449, Nov 16, 2010

Filed:

Apr 30, 2007

Appl. No.:

11/741804

Inventors:

Matthew V. Kaufmann - Morgan Hill CA, US
Teck Yang Tan - Singapore, SG

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/34

US Classification:

257723, 257737, 257738, 257E23079

Abstract:

Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. An IC package includes an IC chip, an insulating layer on the IC chip, a plurality of vias, a plurality of routing interconnects, and a plurality of bump interconnects. The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion and a second portion. The first portion of each routing interconnect is in contact with a respective terminal of the plurality of terminals though a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects.

US Patent:

7872347, Jan 18, 2011

Filed:

Aug 9, 2007

Appl. No.:

11/836606

Inventors:

Matthew V. Kaufmann - Morgan Hill CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/12
H01L 23/48

US Classification:

257700, 257738, 257773, 257783

Abstract:

Methods, systems, and apparatuses for integrated circuit packages, and processes for forming the same, are provided. In one example, an integrated circuit (IC) package includes an integrated circuit die, a layer of insulating material, a redistribution interconnect on the layer of insulating material, and a ball interconnect. The integrated circuit die has a plurality of terminals on a first surface. The insulating material covers the first surface of the die and fills a space adjacent to one or more sides of the die. The redistribution interconnect has a first portion coupled to a terminal of the die through the first layer, and a second portion that extends away from the first portion over the insulating material filling the space adjacent to the die. The ball interconnect is coupled to the second portion of the redistribution interconnect.

US Patent:

8269321, Sep 18, 2012

Filed:

Aug 28, 2007

Appl. No.:

11/897036

Inventors:

Ken Jian Ming Wang - San Francisco CA, US
Matthew Vernon Kaufmann - Morgan Hill CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/495

US Classification:

257666, 257670, 257673, 257E23031, 257E23039

Abstract:

According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die.

US Patent:

8502396, Aug 6, 2013

Filed:

Dec 8, 2008

Appl. No.:

12/330336

Inventors:

Mark Buer - Payson AZ, US
Matthew Kaufmann - Morgan Hill CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/49

US Classification:

257784, 257679, 257776, 257786, 257922, 257E23141, 257E23176

Abstract:

Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.

US Patent:

8508054, Aug 13, 2013

Filed:

Jun 16, 2011

Appl. No.:

13/162233

Inventors:

Mengzhi Pang - Irvine CA, US
Matthew Kaufmann - Morgan Hill CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/52
H01L 23/48
H01L 29/40

US Classification:

257778, 257E2302, 257738, 257780, 438108, 438109

Abstract:

An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.

US Patent:

8643164, Feb 4, 2014

Filed:

Jul 30, 2009

Appl. No.:

12/512313

Inventors:

Matthew Vernon Kaufmann - Morgan Hill CA, US
Teck Yang Tan - Singapore, SG

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/02

US Classification:

257686, 257692, 257E21499

Abstract:

Methods, systems, and apparatuses for wafer-level package-on-package structures are provided herein. A wafer-level integrated circuit package that includes at least one die is formed. The wafer-level integrated circuit package includes redistribution interconnects that redistribute terminals of the die over an area that is larger than an active-surface of the die. Electrically conductive paths are formed from the redistribution interconnects at a first surface of the wafer-level integrated circuit package to electrically conductive features at a second surface of the wafer-level integrated circuit package. A second integrated circuit package may be mounted to the second surface of the wafer-level integrated circuit package to form a package-on-package structure. Electrical mounting members of the second package may be coupled to the electrically conductive features at the second surface of the wafer-level integrated circuit package to provide electrical connectivity between the packages.

US Patent:

20060192297, Aug 31, 2006

Filed:

Apr 26, 2005

Appl. No.:

11/114418

Inventors:

Matthew Kaufmann - Morgan Hill CA, US
Morteza Afghahi - Coto de Caza CA, US

International Classification:

H01L 23/48

US Classification:

257780000

Abstract:

In one embodiment, a die arrangement is disclosed in which a wire-bond pad may be operatively coupled to a power supply via a wire bond. A first pad may be operatively coupled to the wire-bond pad. A second pad may be operatively coupled to the first pad via a redistribution layer.