Matthew P Elwood

US Patent:

7447882, Nov 4, 2008

Filed:

Apr 20, 2005

Appl. No.:

11/109957

Inventors:

Matthew Paul Elwood - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/00

US Classification:

712238

Abstract:

A branch target buffer is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries within the branch target buffer and those individual entries are invalidated.

US Patent:

7447885, Nov 4, 2008

Filed:

Apr 20, 2005

Appl. No.:

11/109956

Inventors:

Matthew Paul Elwood - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/00

US Classification:

712240, 712238, 712239

Abstract:

A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and stored into a prediction value store. The one or more prediction values to be used with a potential branch instruction are selected from the prediction values store using a multiplexer switched by a branch predicting portion of a fetch address. The history buffer is only read when the history value changes whereas the prediction values store is read each time a potential branch instruction is identified requiting a prediction value to be associated with it. The reduced duty cycle of the history buffer saves power.

US Patent:

7793078, Sep 7, 2010

Filed:

Apr 1, 2005

Appl. No.:

11/095655

Inventors:

Matthew Paul Elwood - Austin TX, US
David John Butcher - King's Lynn, GB
Richard Roy Grisenthwaite - Nr Royston, GB

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/30

US Classification:

712209, 712234

Abstract:

A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditional branch instructions provided within the two different instruction sets are arranged to use the same instruction encoding.

US Patent:

20050257037, Nov 17, 2005

Filed:

May 4, 2005

Appl. No.:

11/121184

Inventors:

Matthew Elwood - Austin TX, US
Vladimir Vasekin - Waterbeach, GB

Assignee:

ARM Limited - Cambridge

International Classification:

G06F009/00

US Classification:

712242000

Abstract:

A data processing apparatus and method are disclosed. The data processing apparatus comprises: an instruction fetching circuit operable to fetch a sequence of program instructions from a sequence of memory locations; an instruction decoder responsive to program instructions within the sequence of program instructions fetched by the instruction fetching circuit to control data processing operations specified by the program instructions; and an execution circuit operable under control of the instruction decoder to execute the data processing operations, wherein the instruction decoder is responsive to an execute block instruction within the sequence of program instructions to trigger fetching of a block of two or more program instructions by the instruction fetching circuit and execution of the block of two or more program instructions by the execution circuit, the block of two or more instructions containing a number of program instructions specified by a block length field within the executed block instruction and being stored at a memory location specified by a location field within the execute block instruction, the apparatus further comprises execute block instruction logic operable in response to the execute block instruction to store an indication of a memory location of an instruction following the execute block instruction and to determine which instruction in the block of two or more program instructions is being processed, the execute block instruction logic being further operable when it is determined that a last instruction in the block of two or more program instructions is being processed to provide to the instruction fetching circuit the indication of the memory location of the instruction following the execute block instruction so that the instruction following the execute block instruction is fetched for execution immediately following the last instruction in the block of two or more program instructions. Providing the indication of the memory location of the instruction following the execute block instruction to the instruction fetching circuit causes the fetch unit to fetch that instruction so that the correct sequence of instructions is fetched by the fetch unit which avoids the need to flush instructions.

US Patent:

20060112262, May 25, 2006

Filed:

Nov 22, 2004

Appl. No.:

10/994179

Inventors:

Matthew Elwood - Austin TX, US

Assignee:

ARM LIMITED - Cambridge

International Classification:

G06F 9/00

US Classification:

712240000

Abstract:

A data processing system includes an instruction pipeline with a branch prediction mechanism. The branch prediction mechanism includes a branch history register operating to store a value GHV which can be used to identify whether a newly encountered branch instruction is one which has been previously encountered. If the branch is not one which has previously been encountered, then a not taken prediction is made. This not taken prediction is applied to both conditional and unconditional branch instructions. The instruction set of the processor core supports predication instructions which render unconditional branch instructions conditional.

US Patent:

62162225, Apr 10, 2001

Filed:

May 14, 1998

Appl. No.:

9/078595

Inventors:

Christopher Neal Hinds - Austin TX
David Vivian Jaggar - Austin TX
David Terrence Matheny - Austin TX
Matthew Paul Elwood - Austin TX

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 9302

US Classification:

712244

Abstract:

A data processing apparatus and method is provided, the apparatus comprising an execution unit having a plurality of pipelined stages for executing instructions, such that a maximum of `n` instructions can be being executed simultaneously within the execution unit. Further, a set of at least `n` logical exception registers are provided, each exception register being capable of storing a number of exception attributes associated with an instruction for which an exception has been detected during execution by the execution unit. In the event of an exception being detected during execution of a first instruction, the execution unit is arranged to: (i) store in a first of said exception registers said exception attributes associated with said first instruction; and (ii) to continue executing any remaining instructions already in the pipelined stages at the time the exception was detected. The execution unit is further arranged to store in said exception registers the exception attributes associated with any of the remaining instructions for which an exception is detected during execution, whereby the exception attributes stored in the exception registers can be provided to an exception processing tool for use in recovering from any exceptions occurring during processing of said first instruction and said remaining instructions. By this approach, when the exception processing tool is invoked, then it can deal with any exceptions arising from the instructions executed by the pipeline, and the data processing apparatus can then continue with the next instruction, without the need to re-execute any of the instructions that were in the pipeline at the time the first exception was detected.

US Patent:

63321866, Dec 18, 2001

Filed:

Aug 28, 1998

Appl. No.:

9/143449

Inventors:

Matthew Paul Elwood - Austin TX
Christopher Neal Hinds - Austin TX

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 1200

US Classification:

711217

Abstract:

A floating point unit 26 is provided with a register bank 38 comprising 32 registers that may be used as either vector registers V or scalar registers S. Data values are transferred between memory 30 and the registers within the register bank 38 using contiguous block memory access instructions. Vector processing instructions specify a sequence of processing operations to be performed upon data values within a sequence of registers. The register address is incremented between each operation by an amount controlled by a stride value. Accordingly, the register address can be incremented by values such as 0, 1, 2 or 4 between each iteration. This provides a mechanism for retaining block memory access instructions to contiguous memory addresses whilst supporting vector matrix and/or complex operations in which the data values needed for each iteration are not adjacent to one another in the memory 30.

US Patent:

63049635, Oct 16, 2001

Filed:

Aug 31, 1998

Appl. No.:

9/144175

Inventors:

Matthew Paul Elwood - Austin TX

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 900

US Classification:

712244

Abstract:

The data processing apparatus and method comprises an instruction decoder for decoding a vector instruction representing a sequence of data processing operations, and an execution unit comprising a plurality of pipelined stages for executing said sequence of data processing operations. The execution unit includes exception determination logic for determining, as each instruction enters a predetermined pipelined stage, whether that data processing operation is an exceptional operation matching predetermined exception criteria, the execution unit being arranged to halt processing of said exceptional operation. Further, an exception register is provided for storing exception attributes relating to said exceptional operation, said exception attributes indicating which data processing operation in said sequence has been determined to be said exceptional operation. This enables the exception attributes stored in the exception register to be provided to an exception processing tool for use in handling said exceptional operation. By this approach, it is possible for an exception processing tool to be used to handle the specific exceptional operation that has given rise to the exception condition, rather than providing the entire vector instruction for handling by the exception processing tool.