Matthew A Bonn

US Patent:

6620013, Sep 16, 2003

Filed:

Sep 28, 2001

Appl. No.:

09/968052

Inventors:

Matthew A. Bonn - Saratoga CA

Assignee:

Candescent Technologies Corporation - San Jose CA

International Classification:

H01J 902

US Classification:

445 24, 445 58

Abstract:

One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a passivation layer masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required passivation layer masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time. Advantageously, this increases efficiency and productivity, correspondingly reducing fabrication costs and unit costs of finished devices.

US Patent:

6677705, Jan 13, 2004

Filed:

Sep 28, 2001

Appl. No.:

09/968221

Inventors:

Kazuo Kikuchi - Yokohama, JP
Matthew A. Bonn - Saratoga CA

Assignee:

Candescent Intellectual Property Services Inc. - Los Gatos CA
Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

International Classification:

H01J 546

US Classification:

313495, 313309, 445 24

Abstract:

One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a direct via masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required direct via masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time. Advantageously, this increases efficiency and productivity, correspondingly reducing fabrication costs and unit costs of finished devices.

US Patent:

6710525, Mar 23, 2004

Filed:

Oct 19, 1999

Appl. No.:

09/421781

Inventors:

Jueng Gil Lee - Cupertino CA
Christopher J. Spindt - Menlo Park CA
Johan Knall - Sunnyvale CA
Matthew A. Bonn - Saratoga CA
Kishore K. Chakravorty - San Jose CA

Assignee:

Candescent Technologies Corporation - San Jose CA
Candescent Intellectual Property Services, Inc. - Los Gatos CA

International Classification:

H01J 102

US Classification:

313309, 313495, 313311, 313306

Abstract:

An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.

US Patent:

6734620, May 11, 2004

Filed:

Dec 12, 2001

Appl. No.:

10/017656

Inventors:

Steven J. Radigan - Fremont CA
Matthew A. Bonn - Saratoga CA
Hidenori Kemmotsu - San Jose CA
Theodore S. Fahlen - San Jose CA

Assignee:

Candescent Technologies Corporation - Los Gatos CA
Candescent Intellectual Property Services, Inc. - Los Gatos CA
Sony Corporation - Tokyo

International Classification:

H01J 130

US Classification:

313497, 313310, 445 24

Abstract:

An electron-emitting device ( , or ) contains an electrode, either a control electrode ( ) or an emitter electrode ( ), having a specified portion situated off to the side of the bulk of the electrode. For a control electrode, the specified portion is an exposure portion ( EA or EB) having openings that expose electron-emissive elements ( A or B) situated over an emitter electrode. For an emitter electrode, the specified portion is an emitter-coupling portion situated below at least one electron-emissive element exposed through at least one opening in a control electrode. Configuring the device in this way enables the control-electrode-to-emitter-electrode capacitance to be quite small, thereby enhancing the devices switching speed. If the specified portion of the electrode becomes short circuited to the other electrode, the short-circuit defect can be removed by severing the specified portion from the remainder of its electrode.

US Patent:

6764366, Jul 20, 2004

Filed:

Oct 31, 2001

Appl. No.:

09/999755

Inventors:

Jueng Gil Lee - Cupertino CA
Christopher J. Spindt - Menlo Park CA
Johan Knall - Sunnyvale CA
Matthew A. Bonn - Saratoga CA
Kishore K. Chakravorty - San Jose CA

Assignee:

Candescent Intellectual Property Services, Inc. - Los Gatos CA
Candescent Technologies Corporation - Los Gatos CA

International Classification:

H01J 902

US Classification:

445 24, 445 50

Abstract:

An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.

US Patent:

6844663, Jan 18, 2005

Filed:

May 31, 2000

Appl. No.:

09/588115

Inventors:

Jueng Gil Lee - Cupertino CA, US
Christopher J. Spindt - Menlo Park CA, US
Johan Knall - Sunnyvale CA, US
Matthew A. Bonn - Saratoga CA, US
Kishore K. Chakravorty - San Jose CA, US

Assignee:

Candescent Intellectual Property - San Jose CA

International Classification:

H01J 102

US Classification:

313309, 313495, 313310, 313311, 313306, 445 24

Abstract:

A structure for a multilayer electrode. Specifically, in one embodiment, a multilayer electrode for a flat panel display device is disclosed. The multilayer electrode comprises a metal alloy layer and a protective layer. The metal alloy layer includes neodymium having a concentration of between greater than three atomic percent and six atomic percent. The protective layer is disposed above the metal alloy layer to form a multilayer stack. The multilayer stack is etched to form the multilayer electrode.

US Patent:

6923918, Aug 2, 2005

Filed:

Sep 28, 2001

Appl. No.:

09/968186

Inventors:

Matthew A. Bonn - Saratoga CA, US
Hidenori Kemmotsu - San Jose CA, US
Kazuo Kikuchi - Yokohama, JP

Assignee:

Candescent Intellectual Property Services, Inc. - Los Gatos CA
Candescent Technologies Corporation - Los Gatos CA
Sony Corporation - Tokyo

International Classification:

H01B013/00
G02F001/136
H01L021/44

US Classification:

216 13, 216 84, 438627

Abstract:

The present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. In one embodiment, a novel etchant gas chemistry dispenses with needing a second passivation layer. In one embodiment, a direct via is formed without a separate mask. In one embodiment, access and isolation features of a metallic gate are patterned in the same patterning operation as an associated passivation layer, dispensing with a need for separate patterning of each. In one embodiment, etching is effectuated with high selectivity for nitrides of silicon. In one embodiment, the requirement for at least one passivation layer deposition, a direct via masking step, and separate patterning steps for the passivation layer and metallic gate are eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time. Advantageously, this increases efficiency and productivity, correspondingly reducing fabrication costs and unit costs of finished devices.

US Patent:

46047905, Aug 12, 1986

Filed:

Apr 1, 1985

Appl. No.:

6/718393

Inventors:

Matthew A. Bonn - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2122
H01L 21265

US Classification:

29576B

Abstract:

An improved method is disclosed for isolating active devices in an integrated circuit structure containing both CMOS and bipolar devices to simultaneously form isolation regions to separate CMOS channels from adjacent channels or bipolar devices as well as to separate adjacent bipolar devices from one another. The improved method of isolation also results in the simultaneous formation of a retrograde p-well for the n-channel device. The improved method comprises implanting, into a substrate having field oxide portions previously grown thereon, impurities capable of forming one or more isolation regions, between the active devices, at an energy level sufficiently high to permit penetration of the impurities through the field oxide.