Masood N Murtuza

US Patent:

6849944, Feb 1, 2005

Filed:

May 30, 2003

Appl. No.:

10/449353

Inventors:

Masood Murtuza - Sugar Land TX, US
Muthiah Venkateswaran - Richardson TX, US
Satyendra S. Chauhan - Sugar Land TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348

US Classification:

257734, 257736, 257737, 257738, 438612, 438613, 438614

Abstract:

In one embodiment, an integrated circuit package includes a die associated with an integrated circuit and a die pad. The die has a bottom surface, and the pad has a top surface opposite the bottom surface of the die. Two or more bump pad traces are each coupled to the top surface of the pad, and one or more other traces are each coupled to the top surface of the pad in a corresponding inter-bump pad region between adjacent bump pad traces. A number of solder bumps each couple the die to the pad at a corresponding bump pad trace to provide electrical connectivity between circuitry associated with the die and circuitry associated with the die pad. Each inter-bump pad region is free from any solder mask material deposited to control collapse of the die towards the pad during a reflow process for bonding the die to the pad using the bumps, a supporting structure that contacts the die during the reflow process having been used instead.

US Patent:

6888255, May 3, 2005

Filed:

May 30, 2003

Appl. No.:

10/449212

Inventors:

Masood Murtuza - Sugar Land TX, US
Muthiah Venkateswaran - Richardson TX, US
Satyendra Singh Chauhan - Sugar Land TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L023/48

US Classification:

257778, 257737, 257738, 438613, 22818022

Abstract:

In accordance with the present invention, a built-up bump pad structure and method for the same are provided. The bump pad structure includes a substrate, a bump pad disposed upon the substrate, a solder mask disposed upon the substrate defining an opening around the bump pad, and a conductive material deposited upon the bump pad such that the conductive material at least partially fills the opening around the bump pad.

US Patent:

7790597, Sep 7, 2010

Filed:

Jun 6, 2008

Appl. No.:

12/134337

Inventors:

Satyendra S. Chauhan - Sugar Land TX, US
Rajiv C. Dunne - Murphy TX, US
Gary P. Morrison - Garland TX, US
Masood Murtuza - Sugar Land TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/48
H01L 21/44

US Classification:

438613, 257737, 257738, 257E2301, 257E23023, 257E21476, 438614, 438615, 438616

Abstract:

A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad.

US Patent:

7883936, Feb 8, 2011

Filed:

Nov 16, 2009

Appl. No.:

12/618859

Inventors:

Prema Palaniappan - Ric TX, US
Masood Murtuza - Sugar Land TX, US
Satyendra S Chauhan - Sugar Land TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/50

US Classification:

438107, 438108, 257E21499

Abstract:

In a method and system for fabricating a semiconductor device () having a package-on-package structure, a base laminate substrate (BLS) () is formed to include a base center portion () and a peripheral portion () separated by a barrier element (). The barrier element () forms a peripheral wall () to surround the base center portion (). A frame shaped top laminate substrate (TLS) () is disposed over the peripheral portion () of the BLS (). The TLS () has an open top center portion () matching the base center portion () surrounded by the peripheral wall () to form a cavity (). A plurality of conductive bumps () each disposed between a top contact pad () of the TLS and a base contact pad () of the peripheral portion () of the BLS () are formed to provide electrical and mechanical coupling therebetween. The barrier element () forms a seal between the cavity () and the plurality of conductive bumps ().

US Patent:

8039309, Oct 18, 2011

Filed:

May 7, 2008

Appl. No.:

12/116459

Inventors:

Masood Murtuza - Sugar Land TX, US
Satyendra Singh Chauhan - Sugar Land TX, US
Donald C. Abbott - Norton MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/00

US Classification:

438109, 438112, 438113, 438118, 438124, 438127

Abstract:

A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern.

US Patent:

8643165, Feb 4, 2014

Filed:

Jan 17, 2012

Appl. No.:

13/351579

Inventors:

Darvin R. Edwards - Garland TX, US
Siva Prakash Gurrum - Dallas TX, US
Masood Murtuza - Sugar Land TX, US
Matthew D. Romig - Richardson TX, US
Kazunori Hayata - Beppu-Oita, JP

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/52
H01L 23/48
H01L 23/04
H01L 23/14
H01L 23/06

US Classification:

257690, 257692, 257698, 257702, 257729

Abstract:

A plastic package () in which a semiconductor chip () is adhesively () attached to a metal stripe () having an agglomerate structure, and electrically connected to bondable and solderable metal stripes () having particulate structures; metal stripes () are touching metal stripes () of agglomerate structure to form vertical stacks (); coats of solder () are welded to the agglomerate metal stripes (and ).

US Patent:

20080283992, Nov 20, 2008

Filed:

May 17, 2007

Appl. No.:

11/804237

Inventors:

Prema Palaniappan - Richardson TX, US
Masood Murtuza - Sugar Land TX, US
Satyendra Singh Chauhan - Sugar Land TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/12
H01L 21/50

US Classification:

257686, 438108, 438109, 257E23007, 257E23009, 257E23127, 257E21504, 257E21511

Abstract:

In a method and system for fabricating a semiconductor device () having a package-on-package structure, a base laminate substrate (BLS) () is formed to include a base center portion () and a peripheral portion () separated by a barrier element (). The barrier element () forms a peripheral wall () to surround the base center portion (). A frame shaped top laminate substrate (TLS) () is disposed over the peripheral portion () of the BLS (). The TLS () has an open top center portion () matching the base center portion () surrounded by the peripheral wall () to form a cavity (). A plurality of conductive bumps () each disposed between a top contact pad () of the TLS and a base contact pad () of the peripheral portion () of the BLS () are formed to provide electrical and mechanical coupling therebetween. The barrier element () forms a seal between the cavity () and the plurality of conductive bumps ().

US Patent:

20090297879, Dec 3, 2009

Filed:

May 11, 2009

Appl. No.:

12/463517

Inventors:

Kejun ZENG - Coppell TX, US
Rajiv DUNNE - Murphy TX, US
Masood MURTUZA - Sugar Land TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

B32B 15/16
B32B 15/01
B32B 15/20
B23K 1/20

US Classification:

428647, 428686, 428674, 428675, 428660, 428648, 228176

Abstract:

A solder joint () has a first contact pad and a second contact pad of a first metal, preferably copper, facing each other across a gap. A coat and , respectively) of a second metal, preferably nickel, covers each pad. A layer of crystals of first intermetallic compounds, such as NiSnand (Ni, Cu)Sn, covers the surface of each coat. Isolated crystals of second intermetallic compounds, such as CuSnand (Cu, Ni)Sn, different from the first intermetallic compounds, are dispersed on top of the layer of crystals of the first intermetallic compounds. A solder alloy including a third metal, preferably tin, and the first metal fills the gap. The solder alloy may further include a fourth metal, preferably selected from a group of metals including silver, zinc, and indium.