Silicon Labs
Principal Design Engineer
Silicon Labs Jan 2010 - Jan 2012
Staff Design Engineer
Silicon Labs Jan 2007 - Jan 2010
Senior Design Engineer
Nvidia Oct 2006 - Nov 2006
Hardware Design Engineer
Pmc-Sierra Apr 2005 - Aug 2006
Leader, Product Development
Education:
Virginia Tech 1997 - 1998
Penn State University 1992 - 1995
Master of Science, Masters, Electrical Engineering
Czech Technical University In Prague 1983 - 1988
Skills:
Asic Rtl Design Soc Verilog Static Timing Analysis Ic Debugging Semiconductors Systemverilog Embedded Systems Vlsi Vhdl Tcl Matlab C Pcb Design Digital Electronics Primetime Perl C++ Digital Design Timing Hardware Design Processors Assembly Atpg Simulation