Marlin W Frederick

US Patent:

7221205, May 22, 2007

Filed:

Jul 6, 2004

Appl. No.:

10/883965

Inventors:

Martin Jay Kinkade - Austin TX, US
Marlin Frederick - Cedar Park TX, US

Assignee:

Arm Limited - Cambridge

International Classification:

H03K 3/289

US Classification:

327203, 327213

Abstract:

A clocked scan flip-flop is provided in which a latch within the diagnostic data path is reused to store an operational signal value during a sleep mode. The operational signal value is supplied to the latch via a sleep mode path through a transmission gate (or other tristate driver) controlled by a sleep mode control signal SLP. The diagnostic clock signal SCLK, the operational clock signal CLK and the sleep mode control signal SLP together provide the control operations for controlling the various elements within the clocked-scan flip-flop to move into and out of sleep mode.

US Patent:

7248508, Jul 24, 2007

Filed:

Jan 11, 2006

Appl. No.:

11/329396

Inventors:

Marlin Frederick - Cedar Park TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G11C 11/40

US Classification:

36518906, 365154

Abstract:

The application discloses a semiconductor memory storage device comprising: a data retention portion comprising latches; a peripheral portion comprising read and write logic; and a power switching device wherein said peripheral portion is operable to be powered by a periphery voltage difference; said data retention portion is operable to be powered by a data retention voltage difference said data retention voltage difference being different to said periphery voltage difference; and in response to a write request signal to write to at least one of said latches output from said peripheral portion to said data retention portion by said write logic, said power switching device is operable to reduce a voltage difference across said at least one of said latches such that a data signal output from said peripheral portion and having a voltage level determined by said periphery voltage difference is able to write to said at least one of said latches.

US Patent:

7745275, Jun 29, 2010

Filed:

Sep 10, 2008

Appl. No.:

12/232107

Inventors:

Gregory Munson Yeric - Austin TX, US
Marlin Wayne Frederick - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

H01L 21/336
H01L 29/76

US Classification:

438197, 438637, 438672, 257368, 257385

Abstract:

A method of forming an integrated circuit provides over a diffusion region on a substrate a gate electrode. A source electrode is provided by a source local interconnect conductor and a drain electrode is provided by a drain local interconnect conductor. An insulator layer is formed over these electrodes and respective electrode openings are formed through the insulator layer so as to provide electrical connection to a Metal1 layer. The etching process for the electrode openings is controlled such that the maximum etching depth is insufficient to penetrate through the insulating layer and accordingly short circuit a gate insulator layer provided between the diffusion region and the gate electrode. Thus, the gate opening may be positioned over the diffusion region. Double patterning followed by separate etching steps for the gate opening and the source/drain opening may be used to control the gate opening depth and permit the gate contact to be position overlying the diffusion region.

US Patent:

7893722, Feb 22, 2011

Filed:

Sep 11, 2008

Appl. No.:

12/232187

Inventors:

Stephen Andrew Kvinta - Cedar Park TX, US
Marlin Wayne Frederick - Austin TX, US
Chih-Wei Huang - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

H03K 19/096
H03K 3/00
G01R 31/28

US Classification:

326 96, 327218, 714732

Abstract:

State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry at its functional input and tristate scan signal insertion circuitry for inserting scan data. The tristate scan signal insertion circuitry is controlled by a first clock signal nclk and a second clock signal bclk. The tristate inverter circuitry is controlled by a third clock signal nfclk and a fourth clock signal flck. The clock generating circuitry holds the third and fourth clock signals at fixed values which tristate the tristate inverter circuitry when in scan mode. This moves scan control logic out of the function path comprising the tristate inverter circuitry into the clock control circuitry.

US Patent:

7960759, Jun 14, 2011

Filed:

Oct 14, 2008

Appl. No.:

12/285795

Inventors:

Marlin Wayne Frederick - Austin TX, US
David Paul Clark - Georgetown TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

H01L 23/52

US Classification:

257208, 257E27108

Abstract:

A circuit is provided comprising a first diffusion region and a parallel second diffusion region. A sequence of N gate layers is provided with a first and an Nth of these gate layers covering different respective ones of the diffusion regions whilst the middle (N−2) gate layers cover both diffusion regions. A bridging conductor connects the first gate layer and the Nth gate layer. In some embodiments, the second diffusion region is provided as two second diffusion sub-regions having a diffusion region gap therebetween and electrically connected via a jumper connector. A first gate layer which forms a gate electrode with a first diffusion region can extend through this diffusion region gap not forming a gate electrode therewith and facilitating use of a collinear bridging conductor to connect to the Nth gate layer.

US Patent:

8051390, Nov 1, 2011

Filed:

Oct 7, 2008

Appl. No.:

12/285515

Inventors:

Marlin Wayne Frederick - Austin TX, US
David Paul Clark - Georgetown TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 17/50

US Classification:

716 54, 716 50, 716 51, 716 52, 716 53, 716 55, 716139, 430 5, 430 30

Abstract:

A method of design of a standard cell and a standard cell is disclosed. The method design comprising the steps of: identifying a non-uniformity in a boundary condition of said standard cell that would affect a characteristic of a neighbouring standard cell; introducing a further non-uniformity into said cell to mitigate the effect of said identified non-uniform boundary condition on said characteristic of said neighbouring standard cell.

US Patent:

8051400, Nov 1, 2011

Filed:

Oct 21, 2008

Appl. No.:

12/289159

Inventors:

Marlin Wayne Frederick - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 17/50

US Classification:

716119, 716118, 716122, 716125

Abstract:

A layout for an integrated circuit includes standard cells positioned at standard cell sites. Programmable cells are positioned at programmable fill sites which have a size sufficient to accommodate the programmable cells and are not occupied by standard cells. The position of these programmable sites is recorded in site data as part of the layout data associated with the layout. Empty standard cell sites remaining after standard cells and programmable cells have been placed are filled with standard fill cells. The boundaries of the programmable cells are not constrained other than by alignment with standard cell sites. This permits a high density of programmable fill sites and programmable cells to be achieved. When it is desired to replace a programmable cell with a programmed cell the programmable cells are all deleted from the layout and then the required programmed cells are subject to an automated placement algorithm to place them where appropriate for their function. The remaining empty programmable fill sites are then refilled with programmable cells.

US Patent:

8051401, Nov 1, 2011

Filed:

Oct 15, 2008

Appl. No.:

12/285889

Inventors:

Marlin Wayne Frederick - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 17/50

US Classification:

716129, 716126, 716130, 716133

Abstract:

A technique for generating a layout of an integrated circuit places standard cells in position and provides power rail conductors formed in a second metal layer overlying power connection conductors formed in a first metal layer via which the power is supplied to the standard cells. Routing connection conductors are added in the first metal layer and are permitted to pass through gaps between the power connection conductors of the first metal layer and underneath the power rail conductors of the second metal layer. Once routing has been performed, gaps between the power connection conductors of the first metal layer underlying the power rail conductors and not being used by routing connection conductors are closed so as form interrupted power rail conductors within the first meal layer.