Mark R Visokay

US Patent:

6380080, Apr 30, 2002

Filed:

Mar 8, 2000

Appl. No.:

09/520492

Inventors:

Mark R. Visokay - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2144

US Classification:

438681, 438686, 438778, 427 99, 42725528

Abstract:

The present invention provides methods for the preparation of ruthenium metal films from liquid ruthenium complexes of the formula (diene)Ru(CO) , wherein âdieneâ refers to linear, branched, or cyclic dienes, bicyclic dienes, tricyclic dienes, fluorinated derivatives thereof, combinations thereof, or derivatives thereof additionally containing heteroatoms such as halide, Si, S, Se, P, As, N, or O, in the presence of an oxidizing gas.

US Patent:

6444542, Sep 3, 2002

Filed:

Apr 3, 2001

Appl. No.:

09/826283

Inventors:

Theodore S. Moise - Los Altos CA
Guoqiang Xing - Plano TX
Mark Visokay - Boise ID
Justin F. Gaynor - San Jose CA
Stephen R. Gilbert - San Francisco CA
Francis Celii - Dallas TX
Scott R. Summerfelt - Cupertino CA
Luigi Colombo - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2176

US Classification:

438448, 438553

Abstract:

A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

US Patent:

6482736, Nov 19, 2002

Filed:

Jun 8, 2000

Appl. No.:

09/590791

Inventors:

Cem Basceri - Boise ID
Mark Visokay - Richardson TX
Thomas M. Graettinger - Boise ID
Steven D. Cummings - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2120

US Classification:

438650, 438381, 438686

Abstract:

An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used.

US Patent:

6492241, Dec 10, 2002

Filed:

Apr 10, 2000

Appl. No.:

09/546492

Inventors:

Howard E. Rhodes - Boise ID
Mark Visokay - Boise ID
Tom Graettinger - Boise ID
Dan Gealy - Kuna ID
Gurtej Sandhu - Boise ID
Cem Basceri - Boise ID
Steve Cummings - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2972

US Classification:

438386, 438210, 438387, 438389, 438391, 438399, 438692, 438759, 257296, 257298, 257300, 257532

Abstract:

A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuO ) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

US Patent:

6511896, Jan 28, 2003

Filed:

Apr 6, 2001

Appl. No.:

09/827759

Inventors:

Cem Basceri - Boise ID
Garo J. Derderian - Boise ID
Mark R. Visokay - Richardson TX
John M. Drynan - Boise ID
Gurtej S. Sandhu - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2146

US Classification:

438459, 438656, 438689

Abstract:

In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta O comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta O comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta O comprising layer over a semiconductive substrate. The layer is exposed to WF under conditions effective to etch substantially amorphous Ta O from the substrate. In one implementation, the layer is exposed to WF under conditions effective to both etch substantially amorphous Ta O from the substrate and deposit a tungsten comprising layer over the substrate during the exposing.

US Patent:

6518610, Feb 11, 2003

Filed:

Feb 20, 2001

Appl. No.:

09/789335

Inventors:

Haining Yang - Boise ID
Dan Gealy - Kuna ID
Gurtej S. Sandhu - Boise ID
Howard Rhodes - Boise ID
Mark Visokay - Richardson TX

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 27108

US Classification:

257295, 257306

Abstract:

A structure and method are disclosed for forming a capacitor for an integrated circuit. The capacitor includes a rhodium-rich structure, a rhodium oxide layer in direct contact with the rhodium-rich structure, a capacitor dielectric in direct contact with the rhodium oxide layer and a top electrode over the capacitor. The rhodium-rich structure can include rhodium alloys and the capacitor dielectric preferably has a high dielectric constant.

US Patent:

6544906, Apr 8, 2003

Filed:

Oct 25, 2001

Appl. No.:

10/011219

Inventors:

Antonio L. P. Rotondaro - Dallas TX
Mark R. Visokay - Richardson TX
Luigi Colombo - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21469

US Classification:

438785

Abstract:

A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650Â C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600Â C. while the gate dielectric layer is in the ambient.

US Patent:

6596583, Jul 22, 2003

Filed:

Oct 29, 2001

Appl. No.:

10/002906

Inventors:

Vishnu K. Agarwal - Boise ID
Garo Derderian - Boise ID
Gurtej S. Sandhu - Boise ID
Weimin M. Li - Boise ID
Mark Visokay - Richardson TX
Cem Basceri - Boise ID
Sam Yang - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 218242

US Classification:

438255, 438250

Abstract:

Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500Â C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient.