Mark W Semmelmeyer

US Patent:

20130187292, Jul 25, 2013

Filed:

Jan 20, 2012

Appl. No.:

13/354967

Inventors:

Mark Semmelmeyer - Sunnyvale CA, US
Sandeep Kumar Goel - San Jose CA, US

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu

International Classification:

H01L 23/52
H01L 21/50

US Classification:

257777, 438109, 257E23141, 257E21499

Abstract:

A structure comprises a first die, a second die, an interposer, a third die, and a fourth die. The first die and the second die each have a first surface and a second surface. First conductive connectors are coupled to the first surfaces of the first and second dies, and second conductive connectors are coupled to the second surfaces of the first and second dies. The interposer is over the first and second dies. A first surface of the interposer is coupled to the first conductive connectors, and a second surface of the interposer is coupled to third conductive connectors. The third and fourth dies are over the interposer and are coupled to the third conductive connectors. The first die is communicatively coupled to the second die through the interposer, and/or the third die is communicatively coupled to the fourth die through the interposer.

US Patent:

53815432, Jan 10, 1995

Filed:

Mar 3, 1994

Appl. No.:

8/206563

Inventors:

James S. Blomgren - San Jose CA
Mark Semmelmeyer - Sunnyvale CA
Tuan Luong - San Jose CA
Gary Baum - San Jose CA

Assignee:

Chips and Technologies Inc. - San Jose CA

International Classification:

G06F 106

US Classification:

395550

Abstract:

The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i. e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i. e.

US Patent:

50954245, Mar 10, 1992

Filed:

Jul 21, 1989

Appl. No.:

7/384867

Inventors:

Gary A. Woffinden - Scotts Valley CA
Theodore S. Robinson - Cupertino CA
Jeffrey A. Thomas - Cupertino CA
Robert A. Ertl - Santa Clara CA
James P. Millar - Santa Clara CA
Christopher D. Finan - Santa Clara CA
Joseph A. Petolino - Palo Alto CA
Ajay Shah - San Jose CA
Shen H. Wang - San Jose CA
Mark Semmelmeyer - Sunnyvale CA

Assignee:

Amdahl Corporation - Sunnyvale CA

International Classification:

G06F 1202

US Classification:

395425

Abstract:

A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor.

US Patent:

58127992, Sep 22, 1998

Filed:

Jun 7, 1995

Appl. No.:

8/480738

Inventors:

William K. Zuravleff - Mountainview CA
Mark Semmelmeyer - Sunnyvale CA
Timothy Robinson - Boulder Creek CA
Scott Furman - Union City CA

Assignee:

Microunity Systems Engineering, Inc. - Sunnyvale CA

International Classification:

H01J 1300

US Classification:

395308

Abstract:

A non-blocking load buffer for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

US Patent:

58677356, Feb 2, 1999

Filed:

Feb 9, 1998

Appl. No.:

/020859

Inventors:

William K. Zuravleff - Mountainview CA
Mark Semmelmeyer - Sunnyvale CA
Timothy Robinson - Boulder Creek CA
Scott Furman - Union City CA

Assignee:

Microunity Systems Engineering, Inc. - Sunnyvale CA

International Classification:

G06F 1500
G06F 1520

US Classification:

395872

Abstract:

A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

US Patent:

47456051, May 17, 1988

Filed:

Aug 19, 1986

Appl. No.:

6/897922

Inventors:

Gary S. Goldman - San Jose CA
Mark W. Semmelmeyer - Sunnyvale CA

Assignee:

Amadahl Corporation - Sunnyvale CA

International Classification:

G06F 1110

US Classification:

371 49

Abstract:

In a data processing machine that generates a control word and that includes a plurality of registers connected to receive respective copies of the control word for execution in sections of the data processing machine, the present invention provides an apparatus for detecting an error condition in the execution of the control word. The apparatus detects an error in any of the respective copies of the control word. Further, a second means, responsive to the one copy of the control word in one register, is included for analyzing the one copy to identify a class of possible errors. Finally, responsive to the detection of an error in any of the respective copies and to the class of possible errors, a signal is generated indicating an error condition.

US Patent:

53255160, Jun 28, 1994

Filed:

Mar 9, 1992

Appl. No.:

7/848544

Inventors:

James S. Blomgren - San Jose CA
Mark Semmelmeyer - Sunnyvale CA
Tuan Luong - San Jose CA
Gary Baum - San Jose CA

Assignee:

Chips and Technologies Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

395550

Abstract:

The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i. e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i. e.

US Patent:

57375470, Apr 7, 1998

Filed:

Jun 7, 1995

Appl. No.:

8/480739

Inventors:

William K. Zuravleff - Mountainview CA
Mark Semmelmeyer - Sunnyvale CA
Timothy Robinson - Boulder Creek CA
Scott Furman - Union City CA

Assignee:

MicroUnity Systems Engineering, Inc. - Sunnyvale CA

International Classification:

G06F 1336
G06F 922

US Classification:

395292

Abstract:

A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.