Mark Allen Michael

US Patent:

6713357, Mar 30, 2004

Filed:

Dec 20, 2001

Appl. No.:

10/023348

Inventors:

Hai Hong Wang - Fremont CA
Mark W. Michael - Cedar Park TX
Wen-Jie Qi - Austin TX
William G. En - Milpitas CA
John G. Pellerin - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438287, 438230, 438696

Abstract:

The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.

US Patent:

6764917, Jul 20, 2004

Filed:

Dec 20, 2001

Appl. No.:

10/023350

Inventors:

Darin A. Chan - Campbell CA
William G. En - Milpitas CA
John G. Pellerin - Austin TX
Mark W. Michael - Cedar Park TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2176

US Classification:

438406, 438149, 438311, 438516

Abstract:

A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer initially can have the same thickness. A semiconductor device is also disclosed.

US Patent:

6841832, Jan 11, 2005

Filed:

Dec 19, 2001

Appl. No.:

10/021497

Inventors:

William G. En - Milpitas CA, US
Mark W. Michael - Cedar Park TX, US
Hai Hong Wang - Fremont CA, US
Simon Siu-Sing Chan - Saratoga CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976
H01L 31119

US Classification:

257374, 257202, 257203, 257204, 257206

Abstract:

Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.

US Patent:

6867130, Mar 15, 2005

Filed:

May 28, 2003

Appl. No.:

10/445936

Inventors:

Olov B. Karlsson - San Jose CA, US
Simon S. Chan - Saratoga CA, US
William G. En - Milpitas CA, US
Mark W. Michael - Cedar Park TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/4763
H01L021/44

US Classification:

438655, 438649, 438651, 438656, 438659, 438664, 438682, 257414, 257768, 257769, 257770

Abstract:

Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include forming the thin metal silicide layers on the polysilicon gate electrodes and source/drain regions, depositing a dielectric gap filling layer, as by high density plasma deposition, etching back to selectively expose the silicidized polysilicon gate electrodes and resilicidizing the polysilicon gate electrodes to increase the thickness of the metal silicide layers thereon. Embodiments further include resilicidizing the polysilicon gate electrodes including a portion of the upper side surfaces forming mushroom shaped metal silicide layers.

US Patent:

6964875, Nov 15, 2005

Filed:

Oct 13, 2004

Appl. No.:

10/962582

Inventors:

William G. En - Milpitas CA, US
Mark W. Michael - Cedar Park TX, US
Hai Hong Wang - Fremont CA, US
Simon Siu-Sing Chan - Saratoga CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/66

US Classification:

438 14, 438 10, 438 17

Abstract:

Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.

US Patent:

7861195, Dec 28, 2010

Filed:

Jan 30, 2008

Appl. No.:

12/022860

Inventors:

Darin A. Chan - Santa Clara CA, US
Yi Zou - Sunnyvale CA, US
Yuansheng Ma - Santa Clara CA, US
Marilyn Wright - Sunnyvale CA, US
Mark Michael - Cedar Park TX, US
Donna Michael, legal representative - Cedar Park TX, US

Assignee:

Advanced Mirco Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 19, 716 20, 716 21, 430 5, 430 30

Abstract:

The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.