Mark W Kwong

US Patent:

6947056, Sep 20, 2005

Filed:

Mar 25, 2003

Appl. No.:

10/396648

Inventors:

Mark J. Kwong - Santa Clara CA, US

Assignee:

LSI Logic Corporation - Milpitas GA

International Classification:

G09G005/00
G06T001/00

US Classification:

345605, 345428, 345626, 708102

Abstract:

An apparatus generally having a register, an adder circuit and a mask circuit is disclosed. The register may be configured to replace a current value with a new value in response to a clock value. The adder circuit may be configured to generate the new value by adding the current value to a delta value. The mask circuit may be configured to mask at least one value among the delta value, the new value and the clock value in response to a mask value having a plurality of bits.

US Patent:

6993637, Jan 31, 2006

Filed:

Nov 7, 2002

Appl. No.:

10/290585

Inventors:

Mark J. Kwong - Santa Clara CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711167, 711 5, 711106

Abstract:

A memory system for multiple processors includes a unified memory including a plurality of memory banks, and a memory controller coupled to the unified memory. The memory controller receives requests from the multiple processors, each of the requests including information of a memory address. The memory controller selects one of the memory banks by asserting a request signal only for a memory bank including the requested memory address, and provides the requesting processor with a requested memory operation on the selected memory bank.

US Patent:

60761504, Jun 13, 2000

Filed:

Sep 15, 1997

Appl. No.:

8/929613

Inventors:

Mark J. Kwong - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1200
G06F 1300

US Classification:

711168

Abstract:

A cache controller with an improved cache memory refill operation is presented. After a request from a CPU for a word of information and the word is not found in the cache memory, the cache controller starts a refill operation by which a line of information including the requested word is loaded into the cache memory from a main memory. The cache controller keeps track of the CPU requests. When a requested word appears during the refill operation, the CPU is notified to load the requested word as the word is loaded into the cache memory. Furthermore, the cache controller efficiently takes advantage of free cycles in the refill operation. If the CPU has requested a word in the cache memory, the cache controller reads the word from the cache memory so the CPU can load the word during a free cycle.