Mark P Jamieson

US Patent:

6564452, May 20, 2003

Filed:

Sep 14, 2001

Appl. No.:

09/952590

Inventors:

Joseph C. Barrett - El Dorado CA
Mark P. Jamieson - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 330

US Classification:

29832, 29825, 29830, 29840, 29852

Abstract:

A substrate for a plurality of electronic assemblies includes a strip of printed circuit board (PCB) material including a surface and a plurality of segments. Each segment is adapted to receive at least one electronic component and is arranged to be singulated into a plurality of individual electronic assemblies. Each segment has a perimeter portion located generally about the periphery of the segment, with the surface being covered with a solder mask, except for the perimeter portion.

US Patent:

6545351, Apr 8, 2003

Filed:

Mar 27, 2000

Appl. No.:

09/536240

Inventors:

Mark P. Jamieson - Folsom CA
Joseph C. Barrett - El Dorado CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23495

US Classification:

257712, 257737, 257738, 257675, 257676, 257717, 257707, 257713, 257684, 257797, 257796, 257668, 257780, 257782, 257720, 257760, 257718, 361718, 361719, 361720, 361760

Abstract:

An integrated circuit package which includes an integrated circuit that is attached to a first side of a substrate. The package may also have a solder ball and a heat slug that are both attached to a second side of the substrate. The heat slug and solder ball can be attached to a printed circuit board. The heat slug can provide a thermal path from the substrate to the circuit board which has a relatively wide area. The wide area reduces the thermal impedance and the junction temperatures of the integrated circuit for a given amount of heat.

US Patent:

8125087, Feb 28, 2012

Filed:

Feb 20, 2001

Appl. No.:

09/789401

Inventors:

Mark P. Jamieson - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/52

US Classification:

257778, 257774, 257777, 257786

Abstract:

An interconnect routing for a card or interposer or the like, including splines of traces on a first layer and traces on a second layer, with vias connecting between the layers. Outer rows of signals are routed out from a chip on the first layer, while inner rows of signals are viad down to the second layer where they are routed out, then viad back up to the first layer. These outer vias are arranged in an arc, enabling the second layer trace segments to be of a more uniform length. The second layer may also include ground or power plane fingers extending between the splines and viad up to ground or power signals of the chip.

US Patent:

63102986, Oct 30, 2001

Filed:

Dec 30, 1997

Appl. No.:

9/001024

Inventors:

Joseph C. Barrett - El Dorado CA
Mark P. Jamieson - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 103

US Classification:

174250

Abstract:

A substrate for a plurality of electronic assemblies includes a strip of printed circuit board (PCB) material including a surface and a plurality of segments. Each segment is adapted to receive at least one electronic component and is arranged to be singulated into a plurality of individual electronic assemblies. Each segment has a perimeter portion located generally about the periphery of the segment, with the surface being covered with a solder mask, except for the perimeter portion.

US Patent:

60607777, May 9, 2000

Filed:

Jul 21, 1998

Appl. No.:

9/119863

Inventors:

Mark P. Jamieson - Folsom CA
Joseph C. Barrett - El Dorado CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2310

US Classification:

257707

Abstract:

An integrated circuit package which includes an integrated circuit that is attached to a first side of a substrate. The package may also have a solder ball and a heat slug that are both attached to a second side of the substrate. The heat slug and solder ball can be attached to a printed circuit board. The heat slug can provide a thermal path from the substrate to the circuit board which has a relatively wide area. The wide area reduces the thermal impedance and the junction temperatures of the integrated circuit for a given amount of heat.