Mark Alan Anders

Address:

2559 NE Katie Dr, Hillsboro, OR 97124

VIN:

2G2WC58C871121438

Make:

PONTIAC

Model:

GRAND PRIX

Year:

2007

US Patent:

6351150, Feb 26, 2002

Filed:

Sep 11, 2000

Appl. No.:

09/658793

Inventors:

Ram K. Krishnamurthy - Beaverton OR
Mark A. Anders - Hillsboro OR
Atila Alvandpour - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19096

US Classification:

326 98, 326 93, 326 95, 327208, 327407, 327408

Abstract:

A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.

US Patent:

6522186, Feb 18, 2003

Filed:

Jun 27, 2001

Appl. No.:

09/893067

Inventors:

Frank OMahony - San Carlos CA
Mark A. Anders - Hillsboro OR
Krishnamurthy Soumyanath - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 104

US Classification:

327295, 327293, 327297

Abstract:

A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.

US Patent:

6573756, Jun 3, 2003

Filed:

Jul 31, 2001

Appl. No.:

09/919785

Inventors:

Sanu K. Mathew - Hillsboro OR
Mark Anders - Hillsboro OR
Ram Krishnamurthy - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1716

US Classification:

326 96, 326 24

Abstract:

A noise canceling circuit is provided in a dynamic circuit that includes a high fan-in domino gate. The noise canceling circuit decouples noise from neighboring wires in the dynamic circuit that is injected into a wire that controls the domino gate.

US Patent:

6614279, Sep 2, 2003

Filed:

Aug 29, 2001

Appl. No.:

09/941457

Inventors:

Mark A. Anders - Hillsboro OR
Ram K. Krishnamurthy - Portland OR
Krishnamurthy Soumyanath - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03F 345

US Classification:

327291, 327164

Abstract:

A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

US Patent:

6628143, Sep 30, 2003

Filed:

Sep 26, 2001

Appl. No.:

09/965360

Inventors:

Steven K. Hsu - Lake Oswego OR
Mark A. Anders - Hillsboro OR
Sanu K. Mathew - Hillsboro OR
Ram K. Krishnamurthy - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19096

US Classification:

326 95, 326 98, 326121

Abstract:

An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.

US Patent:

6828841, Dec 7, 2004

Filed:

Aug 29, 2003

Appl. No.:

10/652668

Inventors:

Mark A. Anders - Hillsboro OR
Ram K. Krishnamurthy - Portland OR
Krishnamurthy Soumyanath - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03F 345

US Classification:

327291, 327164

Abstract:

A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

US Patent:

6909127, Jun 21, 2005

Filed:

Jun 27, 2001

Appl. No.:

09/893023

Inventors:

Frank O'Mahony - San Carlos CA, US
Mark A. Anders - Hillsboro OR, US
Krishnamurthy Soumyanath - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L027/10

US Classification:

257208, 257776, 327295

Abstract:

A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e. g. , orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

US Patent:

6940313, Sep 6, 2005

Filed:

Jun 29, 2001

Appl. No.:

09/895278

Inventors:

Mark Anders - Hillsboro OR, US
Ram Krishnamurthy - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K019/096

US Classification:

326 97, 327200

Abstract:

In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater hides the pre-charge signal propagated from the front segment from the rear segment while the rear segment is evaluating.