Mario F Velez

US Patent:

7602050, Oct 13, 2009

Filed:

Apr 5, 2006

Appl. No.:

11/399017

Inventors:

Laxminarayan Sharma - San Diego CA, US
Mario Francisco Velez - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H01L 23/48

US Classification:

257666, 257676

Abstract:

The disclosure provides integrated circuit packages including a lead frame having multiple I/O pads positioned proximate to the lead frame perimeter around a central ground paddle, an integrated circuit die having electrically conductive die terminals positioned on the central ground paddle, and multiple ground circuit pads positioned on and in electrical connection with the central ground paddle. Electrically conductive I/O circuit pads are arranged about the die between the ground circuit pads and the I/O pads, each I/O circuit pad electrically connected to one of the I/O pads. Electrically conductive bond wires connect one or more of the die terminals to one or more I/O circuit pads or one or more ground circuit pads. In certain embodiments, the disclosure further provides an integrated circuit positioned to engage the integrated circuit die in electrical connection with the die terminals. The disclosure also relates to methods of packaging an integrated circuit to reduce packaging parasitics.

US Patent:

8633597, Jan 21, 2014

Filed:

Mar 1, 2010

Appl. No.:

12/714918

Inventors:

Fifin Sweeney - San Diego CA, US
Milind P. Shah - San Diego CA, US
Mario Francisco Velez - San Diego CA, US
Damion B. Gastelum - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257778, 257685, 257720, 257678, 257E21006, 257E21077, 257E21499, 257E21503, 257E21511, 257E23051, 257E23101, 438108, 438109, 438612, 438613

Abstract:

In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.

US Patent:

20100327433, Dec 30, 2010

Filed:

Jun 25, 2009

Appl. No.:

12/491568

Inventors:

Fifin Sweeney - San Diego CA, US
Mario Francisco Velez - San Diego CA, US
Yuancheng Christopher Pan - San Diego CA, US
Shiqun Gu - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H01L 23/34
H01L 23/02
H01L 21/00

US Classification:

257724, 257678, 438110, 257E23079, 257E2318, 257E21001

Abstract:

An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor.

US Patent:

20110180926, Jul 28, 2011

Filed:

Jan 28, 2010

Appl. No.:

12/695543

Inventors:

Milind P. Shah - San Diego CA, US
Mario Francisco Velez - San Diego CA, US
Fifin Sweeney - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H01L 23/12
H01L 21/58

US Classification:

257723, 438126, 257E23003, 257E21505

Abstract:

An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.

US Patent:

20110248405, Oct 13, 2011

Filed:

Apr 9, 2010

Appl. No.:

12/757570

Inventors:

Yiming Li - San Diego CA, US
Mario Francisco Velez - San Diego CA, US
Shiqun Gu - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H01L 23/48
H01L 21/768

US Classification:

257773, 438667, 257E21597, 257E23011

Abstract:

A block layer deposited on a substrate before deposition of metal lines and etching of a through via enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate may be used to fabricate through glass vias without undercut from the wet etching shorting metal lines on the glass substrate. The block layer prevents contact between a conductive layer lining the through via with more than one metal line on the substrate. The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias.

US Patent:

20120075216, Mar 29, 2012

Filed:

Sep 16, 2011

Appl. No.:

13/235158

Inventors:

Justin Phelps Black - Santa Clara CA, US
Ravindra V. Shenoy - Dublin CA, US
Evgeni Petrovich Gousev - Saratoga CA, US
Aristotele Hadjichristos - San Diego CA, US
Thomas Andrew Myers - San Diego CA, US
Jonghae Kim - San Diego CA, US
Mario Francisco Velez - San Diego CA, US
Je-Hsiung Jeffrey Lan - San Diego CA, US
Chi Shun Lo - San Diego CA, US

Assignee:

QUALCOMM MEMS TECHNOLOGIES, INC. - San Diego CA

International Classification:

G06F 3/041
H01L 21/02
H03F 3/04
H01L 27/06

US Classification:

345173, 257531, 438381, 330289, 257E21003, 257E27011

Abstract:

This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

US Patent:

20130032385, Feb 7, 2013

Filed:

Aug 3, 2011

Appl. No.:

13/197162

Inventors:

Peng Cheng Lin - San Jose CA, US
Mario Francisco Velez - San Diego CA, US

Assignee:

QUALCOMM MEMS Technologies, Inc. - San Diego CA

International Classification:

H05K 1/18
H05K 3/30

US Classification:

174260, 29841

Abstract:

This disclosure provides systems and methods for forming a metal thin film shield over a thin film cap to protect electromechanical systems devices in a cavity beneath. In one aspect, a dual or multi layer thin film structure is used to seal a electromechanical device. For example, a metal thin film shield can be mated over an oxide thin film cap to encapsulate the electromechanical device and prevent degradation due to wafer thinning, dicing and package assembly induced stresses, thereby strengthening the survivability of the electromechanical device in the encapsulated cavity. During redistribution layer processing, a metal thin film shield, such as a copper layer, is formed over the wafer surface, patterned and metalized.

US Patent:

20130082799, Apr 4, 2013

Filed:

Nov 14, 2011

Appl. No.:

13/295978

Inventors:

Chengjie Zuo - Santee CA, US
Changhan Yun - San Diego CA, US
Chi Shun Lo - San Diego CA, US
Wesley Nathaniel Allen - Lafayette IN, US
Mario Francisco Velez - San Diego CA, US
Jonghae Kim - San Diego CA, US
Sanghoon Joo - Sunnyvale CA, US

Assignee:

QUALCOMM MEMS TECHNOLOGIES, INC. - San Diego CA

International Classification:

H03H 9/58
H01L 41/04

US Classification:

333189, 310367

Abstract:

Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.