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Maria L Cobarruviaz

Deceased

from Gilroy, CA

Also known as:
  • Maria Lucia Cobarruviaz
  • Maria Cobarruviaz
  • Maria Lt Cobarruviaz

Maria Cobarruviaz Phones & Addresses

  • Gilroy, CA
  • Gustine, CA
  • Hollister, CA
  • 10825 Stevens Canyon Rd, Cupertino, CA 95014 • 408 996-9052
  • Los Altos, CA
  • 10433 Duke Dr, Gilroy, CA 95020

Work

  • Position:
    Production Occupations

Education

  • Degree:
    Bachelor's degree or higher

Us Patents

  • Methods For Forming High Density Multi-Chip Carriers

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  • US Patent:
    52003000, Apr 6, 1993
  • Filed:
    Mar 1, 1991
  • Appl. No.:
    7/662860
  • Inventors:
    Jacques Leibovitz - San Jose CA
    Maria L. Cobarruviaz - Cupertino CA
    Kenneth D. Scholz - Palo Alto CA
    Clinton C. Chao - Redwood City CA
  • Assignee:
    Hewlett-Packard Company - Palo Alto CA
  • International Classification:
    H01L 21283
    H01L 21312
  • US Classification:
    430312
  • Abstract:
    A method for fabricating high density multi-chip carriers for integrated circuits includes the steps of forming a circuit pattern on a substrate, depositing a composite metal layer and a photoresist layer over the circuit pattern, forming apertures in the photoresist layer, forming solid metal vias in the apertures and, then, removing the photoresist layer. After removal of the first photoresist layer, a second photoresist layer is deposited over the solid vias and the circuit pattern. With the second photoresist layer in place, unprotected portions of the composite layer are etched away. Then, the second photoresist layer is stripped away. Next, a layer of photosensitive dielectric material is formed over the structure and, finally, sufficient portions of the photosensitive dielectric material are removed to expose the top surfaces of the solid vias.
  • Stacked Solid Via Formation In Integrated Circuit Systems

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  • US Patent:
    50554255, Oct 8, 1991
  • Filed:
    Jun 1, 1989
  • Appl. No.:
    7/360828
  • Inventors:
    Jacques Leibovitz - San Jose CA
    Maria L. Cobarruviaz - Cupertino CA
    Kenneth D. Scholz - Palo Alto CA
    Clinton C. Chao - Redwood City CA
  • Assignee:
    Hewlett-Packard Company - Palo Alto CA
  • International Classification:
    H01L 21283
    H01L 21312
  • US Classification:
    437195
  • Abstract:
    A method of forming solid copper vias in a dielectric layer permits stacked up vias in a multi-layer multi-chip carrier. An conducting layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in a photoresist layer over said lines is filled with copper by electroplating to form a solid via. The via can be polished until its top is flat. Using a photoresist mask, the conductive layer used for electroplating is removed between the lines. A dielectric layer is then formed over the lines and via. A bulge in the dielectric over the via is removed by etching through an aperture defined in a photoresist layer, which is then stripped. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked up vias.
  • Multi-Layer Fabrication In Integrated Circuit Systems

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  • US Patent:
    53995287, Mar 21, 1995
  • Filed:
    Mar 24, 1993
  • Appl. No.:
    8/037476
  • Inventors:
    Jacques Leibovitz - San Jose CA
    Maria L. Cobarruviaz - Cupertino CA
    Kenneth D. Scholz - Palo Alto CA
    Clinton C. Chao - Redwood City CA
  • International Classification:
    H01L 2144
  • US Classification:
    437195
  • Abstract:
    A method for fabricating layers permits the accurate removal of surface material in a multi-layer multi-chip carrier. An intermediate layer of solid vias is deposited over a circuit layer attached to a substrate. The layer can be filled with a dielectric material. The substrate is attached to a substrate holder such that the intermediate layer is exposed, and the substrate holder is placed onto a rotating platen polisher with the intermediate layer facing the platen surface. Tooling presses the intermediate layer against the rotating polishing platen, allowing the substrate holder and substrate to rotate with three degrees of angular freedom, letting the substrate and intermediate layer self-align to the polishing platen in order to uniformly remove material from the intermediate layer surface. A second circuit layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure of circuit layers separated by uniformly thick dielectric and via layers.
  • Controlled Etching Process For Forming Fine-Geometry Circuit Lines On A Substrate

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  • US Patent:
    52214214, Jun 22, 1993
  • Filed:
    Mar 25, 1992
  • Appl. No.:
    7/857209
  • Inventors:
    Jacques Leibovitz - San Jose CA
    Daniel J. Miller - San Francisco CA
    Maria L. Cobarruviaz - Cupertino CA
    John P. Scalia - San Jose CA
    Howard H. Nakano - Corvallis OR
    Clinton C. Chao - Redwood City CA
  • Assignee:
    Hewlett-Packard Company - Palo Alto CA
  • International Classification:
    B44C 122
    C23F 100
  • US Classification:
    156642
  • Abstract:
    A specialized etching method for producing fine-geometry gold circuit structures. Production thereof is accomplished by maintaining a constant gold etching rate. Metal etching normally slows as the amount of dissolved gold (a reaction product of the etching process) increases. To remove the dissolved gold, one method involves cooling the etchant to precipitate a gold complex therefrom. The remaining, recovered etchant is then heated and made available for continued etching. Another method involves a cathode/anode assembly which is immersed in the etchant. Activation of the assembly recovers metallic gold and regenerates the etchant. These methods, when used continuously or periodically in a dip or spray etching system, maintain a constant etching rate. As a result, fine-geometry circuit structures may be accurately produced while minimizing material costs (e. g. etchant use) and minimizing the production of undesirable waste products and disposal expenses associated therewith.
  • Stacked Solid Via Formation In Integrated Circuit Systems

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  • US Patent:
    51622602, Nov 10, 1992
  • Filed:
    Jan 7, 1991
  • Appl. No.:
    7/638885
  • Inventors:
    Jacques Leibovitz - San Jose CA
    Maria L. Cobarruviaz - Cupertino CA
    Kenneth D. Scholz - Palo Alto CA
    Clinton C. Chao - Redwood City CA
  • Assignee:
    Hewlett-Packard Company - Palo Alto CA
  • International Classification:
    H01L 2144
  • US Classification:
    437195
  • Abstract:
    A method of forming solid copper vias in a dielectric layer permits stacked vias in a multi-chip carrier. A dielectric layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in the dielectric layer is filled with copper by deposition to form a hollow via. Using a photoresist mask, the hollow via is filled solid by electroplating a second amount of copper. The photoresist is then stripped and excess copper extending from the via is polished flat. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked vias.
  • Redistribution Layer And Under Bump Material Structure For Converting Periphery Conductive Pads To An Array Of Solder Bumps

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  • US Patent:
    60113146, Jan 4, 2000
  • Filed:
    Feb 1, 1999
  • Appl. No.:
    9/241221
  • Inventors:
    Jacques Leibovitz - San Jose CA
    Ya Yun Zhu - Cupertino CA
    Maria L. Cobarruviaz - Cupertino CA
    Susan J. Swindlehurst - Redwood City CA
    Cheng-Cheng Chang - Palo Alto CA
    Kenneth D. Scholz - Palo Alto CA
  • Assignee:
    Hewlett-Packard Company - Palo Alto CA
  • International Classification:
    H01L 2348
    H01L 2352
    H01L 2940
  • US Classification:
    257781
  • Abstract:
    An integrated circuit redistribution structure. The integrated circuit redistribution structure includes a plurality of conductive pads located on an active side of an integrated circuit. The integrated circuit redistribution structure includes a redistribution layer and an under bump material structure for receiving a solder bump. The redistribution layer can include a first mechanically protective layer which adheres to the active side of the integrated circuit. The redistribution layer includes a plurality of conductive lines in which at least one of the conductive lines is connected to at least one conductive pad. Each conductive line includes an adhesion and diffusion barrier layer, an electrical conductor layer, and a first metallic protective layer. The under bump material structure is formed over at least one conductive line. The under bump material structure includes a solder wettable metal layer formed over the redistribution layer, and a second metallic protective layer for receiving the solder bump.

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