Mandar Suhas Chitnis

US Patent:

20070186205, Aug 9, 2007

Filed:

Jun 13, 2006

Appl. No.:

11/452677

Inventors:

Henry Yu - Palo Alto CA, US
Darren Zacher - Calgary, CA
Mandar Chitnis - Pleasanton CA, US
Varad Joshi - Portland OR, US
Anil Khanna - Beaverton OR, US

International Classification:

G06F 17/50

US Classification:

716 18

Abstract:

Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information.

US Patent:

20100318954, Dec 16, 2010

Filed:

Jun 3, 2010

Appl. No.:

12/793571

Inventors:

Henry Yu - Palo Alto CA, US
Darren Zacher - Calgary, CA
Mandar Chitnis - Pleasanton CA, US
Varad Joshi - Portland OR, US
Anil Khanna - Beaverton OR, US

International Classification:

G06F 17/50

US Classification:

716117

Abstract:

Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information.

US Patent:

20140317583, Oct 23, 2014

Filed:

Apr 16, 2014

Appl. No.:

14/254765

Inventors:

- Wilsonville OR, US
Darren Zacher - Calgary, CA
Mandar Chitnis - Pleasanton CA, US
Varad Joshi - Portland OR, US
Anil Khanna - Beaverton OR, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 17/50

US Classification:

716104

Abstract:

Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information.