Fahd Hinedi - Austin TX Lakshmikant Mamileti - Denver CO
Assignee:
International Business Machines Corporation - Armonk NY Motorola, Inc - Schaumburg IL
International Classification:
G01R 3128
US Classification:
714 43, 714744, 714727
Abstract:
A bus-clock-speed-independent apparatus and method of wrap input/output (I/O) testing of an I/O interface is provided. Launch data is launched in response to a launch clock. A capture clock is derived from the launch clock by delaying the launch clock through a programmable delay. Launch data is wrapped through the I/O interface buffers and captured in response to the capture clock. A initial value of the programmable delay is selected and successively increased or decreased until the launch data is just captured, or just fails to be captured, respectively. The value of the programmable delay when this occurs provides a measure of the limiting speed of the I/O interface.
Voltage Level Translation For An Output Driver System With A Bias Generator
Fahd Hinedi - Austin TX Moises Cases - Austin TX Satyajit Dutta - Austin TX Robert Heath Dennard - New Rochelle NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19094
US Classification:
326 68
Abstract:
Circuit and method aspects are provided for voltage level translation circuit for an output driver. In a circuit aspect, a circuit includes an input mechanism for receiving an internal data signal of a first predetermined voltage range, at least two stacked transistors coupled to the input mechanism, and a bias generator coupled to the input mechanism and the at least two stacked transistors, the bias generator ensuring that the at least two stacked transistors operate below a predetermined maximum device voltage. The circuit further includes an output mechanism coupled to the at least two stacked transistors, the output mechanism providing an external signal of a second predetermined voltage range.
International Business Machines Corporation - Armonk NY
International Classification:
H02H9/00
US Classification:
361 88
Abstract:
An output driver which maintains over voltage protection on individual circuit elements, providing either a level shifted logic high or a floating-state on its output. The output driver includes a latch driven by a set circuit and a reset circuit. The latch output drives an output stage which produces a level shifted logic high when the latch is set and a floating-state when the latch is reset. Minimal voltage is applied across individual circuit elements by supplying power in concurrent incremental voltage levels to the output driver.
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19094 H03K 190185
US Classification:
326 68
Abstract:
With first semiconductor circuitry, a first signal is received having a first voltage between a voltage A and a voltage B. With second semiconductor circuitry, a second signal is output having a second voltage between a voltage C and a voltage D in response to the first signal. C is greater than A, and D is greater than B.
Circuit And Method For Voltage Level Translation Utilizing A Bias Generator
Fahd Hinedi - Austin TX Moises Cases - Austin TX Satyajit Dutta - Austin TX Robert Heath Dennard - New Rochelle NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G05F 156
US Classification:
323282
Abstract:
Circuit and method aspects for translating acceptable voltage levels from an external device to acceptable voltage levels of an internal device are provided. These aspects include coupling an input receiver between the external device and the internal device, the input receiver including a clamp device, and coupling a bias generator to the input receiver at the clamp device, wherein the bias generator ensures proper translation of a high level input signal from the external device by the input receiver. The bias generator further ensures that a predetermined maximum device voltage of the clamp device is not exceeded.
Stacked Pfet Off-Chip Driver With A Latch Bias Generator For Overvoltage Protection
Fahd Hinedi - Austin TX Lakshmikant Mamileti - Cedar Park TX
Assignee:
International Business Machines Corporation - Armonk NY Motorola, Inc. - Schaumburg IL
International Classification:
H02H 322
US Classification:
361111
Abstract:
Series-connected stacked PFETS are employed in an off-chip driver output stage. When the output driver is enabled, the gate of the PFET transistor directly connected to the output is biased by a latch at a voltage level of either one threshold voltage above ground or one threshold voltage below the power supply, depending on the data signal. This provides overvoltage protection even for overshoots and undershoots of one threshold voltage or less, and provides overvoltage protection below the threshold voltages required to activate conventional overvoltage protection devices. Tight tolerances for maximum gate voltages may thus be achieved, and smaller devices having thinner gate oxides utilized in the off-chip drivers of a processor or other device.