Mahmudul Hassan

US Patent:

7733130, Jun 8, 2010

Filed:

Mar 6, 2008

Appl. No.:

12/043935

Inventors:

Mahmudul Hassan - San Carlos CA, US
Tzungren Allan Tzeng - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H03K 19/096

US Classification:

326 96, 327142, 327145

Abstract:

A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal. The system includes circuitry configured to generate a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched. Data is only latched when the pulse is asserted and on a given edge of the first clock signal, and the circuitry is configured to generate the pulse such that the given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal.

US Patent:

8217814, Jul 10, 2012

Filed:

Dec 17, 2010

Appl. No.:

12/971847

Inventors:

Mahmudul Hassan - San Carlos CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

H03M 9/00

US Classification:

341100, 341101

Abstract:

A serial-to-parallel converter includes a sampling unit that may, in response to a serial clock signal, sample a serial data stream and provide an even serial data stream, and an odd serial data stream. The serial-to-parallel converter also includes a strobe generator and a number of latches. The strobe generator generates a plurality of enable signals based upon the serial clock signal. The frequency of a given enable signal corresponds to a fractional multiple of a frequency of the serial clock signal. In response to a particular respective enable signal, each of a first portion of the latches may latch and output a particular respective even data bit. Each of a second portion of the latches may latch and output a particular respective odd data bit. The serial-to-parallel converter further includes a number of output flip-flops to output the data bits in parallel in response to an output clock signal.

US Patent:

8269538, Sep 18, 2012

Filed:

Apr 27, 2010

Appl. No.:

12/768513

Inventors:

Mahmudul Hassan - San Carlos CA, US

Assignee:

MoSys, Inc. - Santa Clara CA

International Classification:

H03L 7/00

US Classification:

327161, 321141, 321145, 375375

Abstract:

Through the use of a multi-step sweep, the present invention is capable of increasing the speed and improving the error resistance of a signal alignment. In a specific embodiment of the invention, a method for the signal alignment of a target signal and an adjustable signal is disclosed. The target signal is sampled using three or more phase shifted versions of the adjustable signal to obtain a group of target signal state values. Next, through reference to the group of target signal state values it is determined that an edge of the target signal lies between a first phase shifted version and a second consecutive phase shifted version. In response, the first phase shifted version is selected as the starting point for a second sweep. During the second sweep, the phase of the first phase shifted version is sequentially adjusted in relatively small incremental steps to minimize the phase difference relative to the target signal.

US Patent:

20070116164, May 24, 2007

Filed:

Nov 22, 2005

Appl. No.:

11/285265

Inventors:

Mahmudul Hassan - Mountain View CA, US

International Classification:

H04L 7/00

US Classification:

375354000

Abstract:

A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal, and which is not an integer multiple of the frequency of the second clock signal. The first clock domain includes circuitry which is configured to generate both the first clock signal and a reference clock signal derived from the source clock signal. The first clock domain is further configured to utilize the first clock signal to sample the reference clock signal, and assert an aligned signal responsive to detecting an edge of the reference clock signal, wherein the aligned signal indicates an edge of the first clock signal is aligned with an edge of the second clock signal.