Luke Y Zhang

US Patent:

6489248, Dec 3, 2002

Filed:

Aug 23, 2001

Appl. No.:

09/938208

Inventors:

Luke Zhang - Santa Clara CA
Ruiping Wang - Fremont CA
Ida Ariani Adisaputro - San Jose CA
Kwang-Soo Kim - Mountain View CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2100

US Classification:

438714, 156345, 216 37, 216 67, 216 79, 438719, 438734, 438735

Abstract:

A substrate having a patterned mask and exposed openings is provided in a process chamber having process electrodes. In a plasma ignition stage, a process gas is provided in the process chamber and is energized by maintaining the process electrodes at a plasma ignition bias power level. In an etch-passivating stage, an etch-passivating material is formed on at least portions of the substrate by maintaining the process electrodes at an etch-passivating bias power level. In an etching stage, the exposed openings on the substrate are etched by maintaining the process electrodes at an etching bias power level.

US Patent:

62913573, Sep 18, 2001

Filed:

Oct 6, 1999

Appl. No.:

9/414329

Inventors:

Luke Zhang - Santa Clara CA
Ruiping Wang - Fremont CA
Ida Ariani Adisaputro - San Jose CA
Kwang-Soo Kim - Mountain View CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2100

US Classification:

438714

Abstract:

A substrate 20 is placed in a process zone 115 of a process chamber 110, process gas is introduced into the process zone 115, and an energized gas is formed in the process zone 115. First process conditions are set to form etch-passivating deposits onto a surface 22 of the substrate 20. Second process conditions are set to etch the surface 22 of the substrate 20. The etch-passivating deposits formed before the etching process improve etching uniformity and reduce etch-rate microloading.

US Patent:

20170098685, Apr 6, 2017

Filed:

Dec 15, 2016

Appl. No.:

15/379991

Inventors:

- Plano TX, US
Steve Radigan - Fremont CA, US
Vance Dunton - San Jose CA, US
Natalie Nguyen - Milpitas CA, US
Luke Zhang - Milpitas CA, US

Assignee:

SanDisk Technologies LLC - Plano TX

International Classification:

H01L 27/24
H01L 45/00

Abstract:

Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

US Patent:

20160064222, Mar 3, 2016

Filed:

Nov 11, 2015

Appl. No.:

14/938637

Inventors:

- Milpitas CA, US
Steve Radigan - Fremont CA, US
Vance Dunton - San Jose CA, US
Natalie Nguyen - Milpitas CA, US
Luke Zhang - Milpitas CA, US

Assignee:

SANDISK 3D LLC - Milpitas CA

International Classification:

H01L 21/28
H01L 27/24

Abstract:

Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

US Patent:

20140248763, Sep 4, 2014

Filed:

Mar 4, 2014

Appl. No.:

14/196904

Inventors:

- Milpitas CA, US
Steve Radigan - Fremont CA, US
Vance Dunton - San Jose CA, US
Natalie Nguyen - Milpitas CA, US
Luke Zhang - Milpitas CA, US

Assignee:

SanDisk 3D LLC - Milpitas CA

International Classification:

H01L 21/28

US Classification:

438591

Abstract:

Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.