Louis C Parrillo

US Patent:

8610099, Dec 17, 2013

Filed:

Aug 15, 2012

Appl. No.:

13/586580

Inventors:

Lidia Vereen - San Ramon CA, US
Bruce Bateman - Fremont CA, US
Louis Parrillo - Austin TX, US
Elizabeth Friend - Sunnyvale CA, US
David Eggleston - San Jose CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

H01L 21/306
H01L 29/86

US Classification:

257 3, 257 2, 257 5, 257E27004, 438692

Abstract:

In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.

US Patent:

20130082228, Apr 4, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/250772

Inventors:

LOUIS PARRILLO - AUSTIN TX, US
RENE MEYER - ATHERTON CA, US
JIAN WU - SAN JOSE CA, US
DAVID EGGLESTON - SAN JOSE CA, US
LIDIA VEREEN - SAN RAMON CA, US

Assignee:

UNITY SEMICONDUCTOR CORPORATION - SUNNYVALE CA

International Classification:

H01L 47/00

US Classification:

257 4, 257E47001

Abstract:

A memory element (ME) including at least one layer of conductive metal oxide (CMO) that includes mobile oxygen ions and including at least two layers of insulating metal oxide (IMO) is disclosed. In one configuration a layer of IMO that is directly in contact with a CMO layer is specifically selected so that a material of the IMO layer is non-reactive with a material of the CMO. In another configuration, at least one pair of adjacent IMO layers are made from materials having different band gaps operative to an generate an internal electric field positioned in the layers and present in the at least two adjacent IMO layers in the absence of electrical power. The internal electric field can be a static electric field. The IMO and/or CMO layers can be deposited in part or in whole using ALD, PEALD, or nano-deposition. The ME can be formed BEOL.

US Patent:

20130210211, Aug 15, 2013

Filed:

Aug 15, 2012

Appl. No.:

13/586094

Inventors:

Lidia Vereen - San Ramon CA, US
Bruce Bateman - Fremont CA, US
David Eggleston - San Jose CA, US
Louis Parrillo - Austin TX, US

International Classification:

H01L 45/00

US Classification:

438382

Abstract:

A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2Fmay be realized.

US Patent:

47660902, Aug 23, 1988

Filed:

Nov 21, 1986

Appl. No.:

6/933631

Inventors:

Gerald A. Coquin - New Providence NJ
William T. Lynch - Summit NJ
Louis C. Parrillo - Warren NJ

Assignee:

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H01L 21425

US Classification:

437 57

Abstract:

A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10. mu. m, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.

US Patent:

46461230, Feb 24, 1987

Filed:

Apr 21, 1986

Appl. No.:

6/857391

Inventors:

William T. Lynch - Summit NJ
Louis C. Parrillo - Warren NJ

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H01L 2702
H01L 2906

US Classification:

357 42

Abstract:

A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10. mu. m, as well as a method for fabricating the device, is disclosed. The inventive CMOS device includes a latchup-preventing, polysilicon-filled trench formed in the semiconductor substrate between the n- and p-channel FETs of the device. The polysilicon-filled trench is essentially free of crack-inducing voids, and achieves a width less than 10. mu. m, because the angle between the trench sidewall and a perpendicular drawn to the substrate surface is greater than, or equal to, about 5 degrees but less than about 10 degrees. Also, a thickness of the polysilicon deposited into the trench is greater than half the width of the trench.

US Patent:

49295659, May 29, 1990

Filed:

Oct 30, 1989

Appl. No.:

7/429953

Inventors:

Louis C. Parrillo - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21265
H01L 2700

US Classification:

437 34

Abstract:

A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level.

US Patent:

47538988, Jun 28, 1988

Filed:

Jul 9, 1987

Appl. No.:

7/071002

Inventors:

Louis C. Parrillo - Austin TX
Stephen S. Poon - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21265

US Classification:

437 44

Abstract:

A process is disclosed for fabricating LDD CMOS structures having a reduced mask count and improved manufacturability. In one embodiment of the invention a CMOS structure is formed having gate insulators overlying N and P type surface regions. Gate electrodes are formed on each of the surface regions and a spacer forming material is deposited over the electrodes and the surface regions. The spacer material is anisotropically etched from one of the surface regions to form spacers at the edge of the first gate electrode while retaining the spacer forming material over the second surface region. Source and drain regions of the first MOS transistor are implanted using the spacers as an implantation mask. The spacers are removed and a lightly doped source and drain is implanted using the gate electrode as a mask. The implanted source and drain regions are oxidized using the remaining spacer forming material as an oxidation mask to prevent oxidation of the second surface region.

US Patent:

47450860, May 17, 1988

Filed:

May 11, 1987

Appl. No.:

7/047589

Inventors:

Louis C. Parrillo - Austin TX
Stephen J. Cosentino - Austin TX
Richard W. Mauntel - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2126
H01L 21265
H01L 2122

US Classification:

437 57

Abstract:

A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.