Lisa Anne Fanti from 44 Monarch Dr, East Fishkill, NY 12533, age 61, Phone: 845 896-7327

Us Patents

Electrochemical Etch For High Tin Solder Bumps
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US Patent:

6468413, Oct 22, 2002
Filed:

Oct 26, 2000
Appl. No.:

09/697333
Inventors:

Lisa A. Fanti - Hopewell Junction NY
John Michael Cotte - New Fairfield CT
David Ely Eichstadt - Wappingers Falls NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

C25F 302
US Classification:

205682, 205684
Abstract:

An aqueous electrochemical etchant for etching metals in the presence of one or more metals not to be etched, the etchant including glycerol in the concentration range of 1. 30 to 1. 70 M, a sulfate compound having a sulfate ion concentration in the range of 0 to 0. 5 M, and a phosphate compound having a phosphate ion concentration in the range of 0. 1 to 0. 5 M.

Sacrificial Seed Layer Process For Forming C4 Solder Bumps
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US Patent:

6622907, Sep 23, 2003
Filed:

Feb 19, 2002
Appl. No.:

10/078948
Inventors:

Lisa A. Fanti - Hopewell Junction NY
Randolph F. Knarr - Goldens Bridge NY
Erik J. Roggeman - Fishkill NY
Kamalesh K. Srivastava - Wappingers Falls NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

B23K 3102
US Classification:

228215, 22818022, 228245, 228256, 438613, 438694, 216 18, 216 41
Abstract:

Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C solder bump openings therethrough with the shape of C solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C solder bump openings to form through holes in the conductive metal layer exposing C solder bump plating sites on the top surface of the base below the C solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C solder bump plating sites. As an option, form a barrier layer over the plating sites next. Form C solder bumps on the plating sites on the base/barrier layer within the C solder bump openings, with the C solder bumps being in contact with the conductive metal layer on the periphery of the through holes.

Inhibition Of Tin Oxide Formation In Lead Free Interconnect Formation
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US Patent:

6900142, May 31, 2005
Filed:

Jul 30, 2003
Appl. No.:

10/604560
Inventors:

Emanual I. Cooper - Scarsdale NY, US
John M. Cotte - New Fairfield CT, US
Lisa A. Fanti - Hopewell Junction NY, US
David E. Eichstadt - Noth Salem NY, US
Stephen J. Kilpatrick - Lagrangeville NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L021/461
US Classification:

438747, 257736, 252 791
Abstract:

A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield. An electroetch is preferred to remove the portion of the seed layer overlying the lower barrier layer.

I/C Chip Suitable For Wire Bonding
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US Patent:

6995475, Feb 7, 2006
Filed:

Sep 18, 2003
Appl. No.:

10/666775
Inventors:

Julie C. Biggs - Wappingers Falls NY, US
Tien-Jen Cheng - Bedford NY, US
David E. Eichstadt - North Salem NY, US
Lisa A. Fanti - Hopewell Junction NY, US
Jonathan H. Griffith - Poughkeepsie NY, US
Randolph F. Knarr - Goldens Bridge NY, US
Sarah H. Knickerbocker - Hopewell Junction NY, US
Kevin S. Petrarca - Newburgh NY, US
Roger A. Quon - Beacon NY, US
Wolfgang Sauter - Richmond VT, US
Kamalesh K. Srivastava - Wappingers Falls NY, US
Richard P. Volant - New Fairfield CT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 23/48
H01L 23/52
H01L 29/40
US Classification:

257784, 257737, 257761, 257766
Abstract:

A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Method Of Forming A Bond Pad On An I/C Chip And Resulting Structure
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US Patent:

7572726, Aug 11, 2009
Filed:

Nov 10, 2005
Appl. No.:

11/271760
Inventors:

Julie C. Biggs - Wappingers Falls NY, US
Tien-Jen Cheng - Bedford NY, US
David E. Eichstadt - North Salem NY, US
Lisa A. Fanti - Hopewell Junction NY, US
Jonathan H. Griffith - Poughkeepsie NY, US
Randolph F. Knarr - Goldens Bridge NY, US
Sarah H. Knickerbocker - Hopewell Junction NY, US
Kevin S. Petrarca - Newburgh NY, US
Roger A. Quon - Beacon NY, US
Wolfgang Sauter - Richmond VT, US
Kamalesh K. Srivastava - Wappingers Falls NY, US
Richard P. Volant - New Fairfield CT, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/44
US Classification:

438617, 438614, 257E21519
Abstract:

A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Method Of Improving Uniformity Of Etching Of A Film On An Article
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US Patent:

20020190028, Dec 19, 2002
Filed:

May 31, 2001
Appl. No.:

09/870534
Inventors:

Kamalesh Srivastava - Wappingers Falls NY, US
Lisa Fanti - Hopewell Junction NY, US
Jonathan Griffith - LaGrangeville NY, US
Randolph Knarr - Poughkeepsie NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

B44C001/22
C23F001/00
US Classification:

216/090000
Abstract:

A method of improving the uniformity of etching of a film on an article, the method including the steps of immersing the article containing the film into a tank of etchant, rotating the article while in the etchant for a desired amount of time so as to cause improved uniformity of etching of the film compared to etching without rotating the article, and removing the article from the tank of etchant. In a preferred embodiment of the invention, the article is a semiconductor wafer.

Process Improvements For Titanium-Tungsten Etching In The Presence Of Electroplated C4'S
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US Patent:

60155051, Jan 18, 2000
Filed:

Oct 30, 1997
Appl. No.:

8/960839
Inventors:

Lawrence D. David - Enfield NH
Lisa A. Fanti - Hopewell Junction NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 2100
US Classification:

252 792
Abstract:

A process and etchant solution for chemical wet etching of thin film metals in the presence of a protected metal. The etching solution has a pH range of about 2. 7 to 4. The etching solution may include hydrogen peroxide, potassium sulfate, and potassium EDTA, and it reduces or eliminates the incidence of etch-resistant metal without damaging the protected metal.

Process For Stabilizing Organic Additives In Electroplating Of Copper
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US Patent:

59354020, Aug 10, 1999
Filed:

Oct 9, 1998
Appl. No.:

9/169294
Inventors:

Lisa A. Fanti - Hopewell Junction NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

C25D 338
US Classification:

205101
Abstract:

A process and assembly for stabilizing organic additives in an electrolytic solution while electroplating copper. The process includes forming a protective film on a first surface of an anode and minimizing contact between the electrolytic solution and a second surface of the anode which is further from the cathode than the first surface. An anode housing is used to minimize contact between the electrolytic solution and the second surface of the anode. The housing includes two side walls and a bottom wall, each having a groove, and a sealing back plate. The anode is fitted in the grooves such that the first surface of the anode is in contact with the electrolytic solution and the second surface of the anode abuts against the sealing back plate. The anode housing may be used in an electroplating system including the anode housing, a plating tank containing the electrolytic solution, a cathode immersed in the electrolytic solution, and an anode, which preferably is in the shape of a slab.