Lily X Springer from Lexington, MA, age 66

Us Patents

Field Effect Transistor With Improved Isolation Structures
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US Patent:

6730569, May 4, 2004
Filed:

Oct 25, 2001
Appl. No.:

10/001432
Inventors:

Lily X. Springer - Dallas TX
Binghua Hu - Plano TX
Chin-Yu Tsai - Plano TX
Jozef C. Mitros - Richardson TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 21336
US Classification:

438298, 438420, 438449, 438451
Abstract:

An electronic device architecture is described comprising a field effect device in an active region of a substrate. Channel stop implant regions and are used as isolation structures and are spaced apart from the active region by extension zones and. The spacing is established by using an inner mask layer and an outer mask layer to define the isolation structures.

Single Poly Eeprom With Reduced Area
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US Patent:

6747308, Jun 8, 2004
Filed:

Dec 30, 2002
Appl. No.:

10/334319
Inventors:

Jozef C. Mitros - Richardson TX
Lily Springer - Dallas TX
Roland Bucksch - Richardson TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 29788
US Classification:

257315, 257239, 257261, 257314, 257316, 438201, 438211, 438257, 438266
Abstract:

An EEPROM ( ) comprises a source region ( ), a drain region ( ); and a polysilicon layer ( ). The polysilicon layer ( ) comprises a floating gate comprising at least one polysilicon finger ( A- E) operatively coupling the source region ( ) and drain region ( ) and a control gate comprising at least one of the polysilicon fingers ( A- E) capacitively coupled to the floating gate. The EEPROM ( ) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.

Field Effect Transistor With Improved Isolation Structures
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US Patent:

6806541, Oct 19, 2004
Filed:

Mar 1, 2004
Appl. No.:

10/791172
Inventors:

Lily X. Springer - Dallas TX
Binghua Hu - Plano TX
Chin-Yu Tsai - Plano TX
Jozef C. Mitros - Richardson TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 2976
US Classification:

257400, 257376, 257398, 257399
Abstract:

An electronic device architecture is described comprising a field effect device in an active region of a substrate. Channel stop implant regions and are used as isolation structures and are spaced apart from the active region by extension zones and. The spacing is established by using an inner mask layer and an outer mask layer to define the isolation structures.

Transistors Formed With Grid Or Island Implantation Masks To Form Reduced Diffusion-Depth Regions Without Additional Masks And Process Steps
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US Patent:

6869851, Mar 22, 2005
Filed:

Jan 20, 2004
Appl. No.:

10/761438
Inventors:

Joe R. Trogolo - Plano TX, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Sheldon Haynie - Amherst NH, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L021/336
H01L021/8836
US Classification:

438301, 438279, 438270
Abstract:

A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.

Single Poly-Emitter Pnp Using Dwell Diffusion In A Bicmos Technology
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US Patent:

6949424, Sep 27, 2005
Filed:

Aug 28, 2003
Appl. No.:

10/650621
Inventors:

Lily Springer - Dallas TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L021/8238
US Classification:

438202, 438369, 438527, 257370
Abstract:

A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

Memory Device With Reduced Cell Size
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US Patent:

6958269, Oct 25, 2005
Filed:

Jun 24, 2002
Appl. No.:

10/178100
Inventors:

Josef Czeslaw Mitros - Richardson TX, US
Imran Khan - Richardson TX, US
Lily Springer - Dallas TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L021/236
H01L029/745
US Classification:

438257, 438258, 438260, 438261, 438593, 438588, 438264, 257213, 257314, 257315, 257319, 257410
Abstract:

A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.

Single Poly-Emitter Pnp Using Dwell Diffusion In A Bicmos Technology
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US Patent:

7164174, Jan 16, 2007
Filed:

Jul 28, 2005
Appl. No.:

11/191788
Inventors:

Lily Springer - Dallas TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 29/732
US Classification:

257370, 257592, 257E29183, 438202
Abstract:

A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

Versatile System For Optimizing Current Gain In Bipolar Transistor Structures
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US Patent:

7226835, Jun 5, 2007
Filed:

Jul 15, 2002
Appl. No.:

10/196634
Inventors:

Joe Trogolo - Plano TX, US
Tathagata Chatterlee - Richardson TX, US
Lily Springer - Dallas TX, US
Jeff Smith - Plano TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H01L 31/0328
US Classification:

438235, 257197, 257198, 257565
Abstract:

Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure () and the required current density throughput of an electrical contact structure () are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.