Li Li S Zhang

Author:

Li Zhang

ISBN #:

0804740305

Author:

Li Zhang

ISBN #:

0804742065

Author:

Li Zhang

ISBN #:

0824750543

Author:

Li Zhang

ISBN #:

7561432429

Author:

Li Zhang

ISBN #:

7801064542

US Patent:

6425070, Jul 23, 2002

Filed:

Mar 18, 1998

Appl. No.:

09/044086

Inventors:

Qiuzhen Zou - San Diego CA
Gilbert C. Sih - San Diego CA
Inyup Kang - San Diego CA
Quaeed Motiwala - San Diego CA
Deepu John - La Jolla CA
Li Zhang - San Diego CA
Haitao Zhang - La Jolla CA

Assignee:

Qualcomm, Inc. - San Diego CA

International Classification:

G06F 9302

US Classification:

712 35, 712210, 712221, 712223, 712 33, 711201, 711212, 710127, 710126

Abstract:

The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention.

US Patent:

6615341, Sep 2, 2003

Filed:

Jun 5, 2001

Appl. No.:

09/876189

Inventors:

Gilbert C. Sih - San Diego CA
Qiuzhen Zou - La Jolla CA
Inyup Kang - San Diego CA
Quaeed Motiwala - San Diego CA
Deepu John - La Jolla CA
Li Zhang - San Diego CA
Haitao Zhang - La Jolla CA
Charles E. Sakamaki - San Diego CA
Prashant A. Kantak - San Diego CA
Sanjay K. Jha - San Diego CA
Jian Lin - San Diego CA

Assignee:

Qualcomm, Inc. - San Diego CA

International Classification:

G06F 9302

US Classification:

712221, 712222, 712 41, 712 33, 712 35, 712 25, 708495, 708204, 708501

Abstract:

A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

US Patent:

6937643, Aug 30, 2005

Filed:

Apr 30, 2002

Appl. No.:

10/137028

Inventors:

Tao Li - San Diego CA, US
Li Zhang - San Diego CA, US

Assignee:

Qualcomm Inc - San Diego CA

International Classification:

H04B001/69

US Classification:

375147, 375145, 375152, 375130, 370321, 370342, 342363, 342357

Abstract:

A device includes a request arbitration unit that (1) receives a number of requests for PN vectors from a number of processing units and (2) provides a control indicative of each request selected for processing. An address generator provides one or more addresses (which may be dependent on a particular PN sequence being requested and the offset of the PN sequence) for each selected request. One or more memory units store all “base” PN sequences (e. g. , and X(i) sequence and a Y(i) sequence defined by W-CDMA) that may be used to generate all requestable PN vectors. The memory unit(s) provide one or more segments of one or more base PN sequences, based on the address(es). A buffering unit provides a set of one or more PN vectors derived from the one or more PN segments for each selected request.

US Patent:

7293232, Nov 6, 2007

Filed:

Nov 26, 2003

Appl. No.:

10/723329

Inventors:

Mikhail Arkhipov - Woodinville WA, US
Joshua Israel Kaplan - Seattle WA, US
Timothy Michael Mc Bride - Snohomish WA, US
Li Zhang - Sammamish WA, US
C. Douglas Hodges - Sammamish WA, US
Elliot H. Omiya - Kirkland WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 9/44

US Classification:

715531, 717143

Abstract:

A source code editor is used to develop multilanguage documents while providing the advanced editing functionality of secondary editors and without requiring the programmer to explicitly open and interface with the secondary editors. The multilanguage document is presented to the user in a primary application view of the primary editor. Code segments written in different languages are identified and sent to the appropriate secondary editors, which in turn create secondary documents that are transparent to the programmer. As edits are made to the primary application view of the document, the edits are replicated by the secondary editors behind the scene. Functionality that is enabled by the secondary editors, such as syntax coloring, auto-completion, and validation is identified by the primary editor and replicated in the primary application view, so as to appear as if the primary editor is inherently configured with the leveraged functionality of the secondary editors.

US Patent:

7307480, Dec 11, 2007

Filed:

Apr 24, 2003

Appl. No.:

10/422271

Inventors:

Li Zhang - San Diego CA, US
Eugene Sy - San Jose CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G01R 23/00
H04Q 7/34

US Classification:

331 44, 370332

Abstract:

Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer. In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control and gain control are iterated to perform gain calibration, with signaling to control the iterations without need for processor intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.

US Patent:

7310367, Dec 18, 2007

Filed:

Oct 17, 2003

Appl. No.:

10/688145

Inventors:

Tao Li - San Diego CA, US
Li Zhang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04B 1/00

US Classification:

375147

Abstract:

An integrated circuit that performs data demodulation on partially despread symbols includes a despreading unit, a channel compensation unit, and a symbol combiner. The despreading unit despreads input samples and provides despread symbols for a first code channel with a first spreading factor. The channel compensation unit multiplies the despread symbols with channel estimates and provides demodulated symbols. The symbol combiner combines groups of demodulated symbols to obtain recovered data symbols for a second code channel with a second spreading factor that is an integer multiple of the first spreading factor. The channel compensation and symbol combining are dependent on whether or not transmit diversity is used. For a TDM design, despread symbols for multiple first code channels are processed in a TDM manner, one channel at a time, to obtain recovered data symbols for multiple second code channels. The channel compensation unit and symbol combiner can be operated in a pipelined manner.

US Patent:

7310623, Dec 18, 2007

Filed:

Dec 12, 2003

Appl. No.:

10/734713

Inventors:

Raymond G. Beausoleil - Redmond WA, US
Tad Hogg - Mountain View CA, US
Li Zhang - Mountain View CA, US
William J. Munro - Bristol, GB

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06E 1/00

US Classification:

706 15, 257 9, 977755, 977762

Abstract:

A quantum approach to the economically significant n-player public goods or similar n-player game requires only two-particle entanglement and is thus much easier to implement than games requiring n-particle entanglements. Two-particle entanglements are sufficient to give near optimal expected payoff when players use a simple mixed strategy for which no player can benefit by making different choices. This mechanism can also address some heterogeneous preferences among the players. Quantum games in accordance with the invention can be simulated on classical computers without requiring impractical amounts of processing power for large numbers of players.

US Patent:

7516441, Apr 7, 2009

Filed:

Jul 21, 2004

Appl. No.:

10/896610

Inventors:

Jennifer A Hamilton - Bellevue WA, US
Michael M Magruder - Issaquah WA, US
James H Hogg - Bellevue WA, US
William G Evans - Woodinville WA, US
Vance P Morrison - Kirkland WA, US
Lawrence B Sullivan - Renton WA, US
Sean E Trowbridge - Sammamish WA, US
Jason L Zander - Sammamish WA, US
Ian H Carmichael - Sammamish WA, US
Patrick H Dussud - Bellevue WA, US
John L Hamby - Issaquah WA, US
John J Rivard - Redmond WA, US
Li Zhang - Sammamish WA, US
Mario Chenier - Woodinville WA, US
Douglas Rosen - Woodinville WA, US
Steven J Steiner - Seattle WA, US
Peter A Hallam - Seattle WA, US
Brian R Crawford - Seattle WA, US
James S Miller - Bellevue WA, US
Sam Spencer - Redmond WA, US
Habib Heydarian - Kirkland WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 9/44

US Classification:

717110, 717153, 714 38, 707103 R

Abstract:

A system and method of providing edit and continue support in a software program debugging environment. “Edit and continue” support allows a user (e. g. , programmer and/or developer) to update the code and/or data structure(s) of an executing program while it is running. After the user has finished editing their code and resumes execution, an integrated development environment (IDE) propagates the edit(s) into a common language runtime (CLR) environment before continuing. Therefore, from the CLR environment's perspective, an edit is a block of intermediate language code (IL) and/or metadata that is inserted into a running process. Moreover, The IDE can facilitate: determining “legality” of an edit; building the edit; sending the edit to the CLR environment; and/or, facilitating the CLR environment switch execution to the edited code.

Address:

24613 SE 9 Pl, Sammamish, WA 98074

Phone:

425 802-0919

VIN:

4JGBF2FE9BA756876

Make:

MERCEDES-BENZ

Model:

GL-CLASS

Year:

2011