Leonard G Douglas

US Patent:

6396153, May 28, 2002

Filed:

Jan 25, 2001

Appl. No.:

09/768598

Inventors:

Raymond Albert Fillion - Niskayuna NY
Ernest Wayne Balch - Ballston Spa NY
Ronald Frank Kolc - Cherry Hill NJ
Robert John Wojnarowski - Ballston Lake NY
Leonard Richard Douglas - Burnt Hills NY
Thomas Bert Gorczyca - Schenectady NY

Assignee:

General Electric Company - Schenectady NY

International Classification:

H01L 2348

US Classification:

257774, 257773

Abstract:

One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

US Patent:

6410356, Jun 25, 2002

Filed:

Mar 7, 2000

Appl. No.:

09/520751

Inventors:

Robert John Wojnarowski - Ballston Lake NY
Ernest Wayne Balch - Ballston Spa NY
Leonard Richard Douglas - Burnt Hills NY

Assignee:

General Electric Company - Schenectady NY

International Classification:

H01L 2166

US Classification:

438 15, 438 14, 438 17, 438125, 438126, 438411, 438619, 438623

Abstract:

A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.

US Patent:

6475877, Nov 5, 2002

Filed:

Dec 22, 1999

Appl. No.:

09/469749

Inventors:

Richard Joseph Saia - Niskayuna NY
Kevin Matthew Durocher - Waterford NY
James Wilson Rose - Guilderland NY
Leonard Richard Douglas - Burnt Hills NY

Assignee:

General Electric Company - Schenectady NY

International Classification:

H01L 21301

US Classification:

438460, 438106, 438461

Abstract:

A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using âadaptive lithographyâ. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost. The method is compatible with the projected designs of the next generation die which will have bond pads on the order of 40 um in size.

US Patent:

6574522, Jun 3, 2003

Filed:

Dec 28, 1999

Appl. No.:

09/473041

Inventors:

Leonard Richard Douglas - Burnt Hills NY

Assignee:

General Electric Company - Niskayuna NY

International Classification:

G06F 1900

US Classification:

700109, 700 65

Abstract:

A system and method for handling quality control data for a manufacturing process among a main computer and a plurality of remote computers, including the steps of establishing a connection between at least one of the remote computers and the main computer via a web browser, inputting quality control data of the manufacturing process from the remote computer into a database of the main computer via the web browser, performing a statistical analysis on the quality control data input into the main computer, and posting results of the statistical analysis on a web site of the main computer accessible to the remote computers through the web browser.

US Patent:

6603145, Aug 5, 2003

Filed:

May 2, 2002

Appl. No.:

10/136626

Inventors:

Robert John Wojnarowski - Ballston Lake NY
Ernest Wayne Balch - Ballston Spa NY
Leonard Richard Douglas - Burnt Hills NY

Assignee:

General Electric Company - Niskayuna NY

International Classification:

H01L 310312

US Classification:

257 77, 257744, 257773

Abstract:

A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.

US Patent:

6790703, Sep 14, 2004

Filed:

Jul 22, 2002

Appl. No.:

10/199296

Inventors:

Richard Joseph Saia - Niskayuna NY
Kevin Matthew Durocher - Waterford NY
James Wilson Rose - Guilderland NY
Leonard Richard Douglas - Burnt Hills NY

Assignee:

General Electric Company - Niskayuna NY

International Classification:

H01L 2158

US Classification:

438107, 29833

Abstract:

A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using âadaptive lithographyâ. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost. The method is compatible with the projected designs of the next generation die which will have bond pads on the order of 40um in size.

US Patent:

6957007, Oct 18, 2005

Filed:

Jul 29, 2002

Appl. No.:

10/064581

Inventors:

Ernest Wayne Balch - Nisakyuna NY, US
Leonard Richard Douglas - Burnt Hills NY, US
Min-Yi Shih - Clifton Park NY, US

Assignee:

General Electric Company - Niskayuna NY

International Classification:

G02B006/00
G03C005/00
G06F019/00

US Classification:

385147, 430321, 700120

Abstract:

A method for adaptively fabricating a waveguide comprises: measuring misplacement of a photonic device relative to a substrate; generating computer readable instructions for using a plurality of graphics primitives to form the waveguide; and photocomposing the waveguide on the substrate in accordance with the computer readable instructions. A reticle comprises a plurality of graphics primitives with at least one of the plurality of graphics primitives comprising a tapered end. A waveguide comprises a plurality of waveguide segments with each of the plurality of waveguide segments comprising a tapered end and being adjacent to at least one other of the plurality of waveguide segments.

US Patent:

7146081, Dec 5, 2006

Filed:

Jul 8, 2005

Appl. No.:

11/178657

Inventors:

Ernest Wayne Balch - Ballston Spa NY, US
Leonard Richard Douglas - Burnt Hills NY, US
Min-Yi Shih - Clifton Park NY, US

Assignee:

General Electric Company - Niskayuna NY

International Classification:

G02B 6/26
G02B 6/02

US Classification:

385 43, 385123

Abstract:

A method for adaptively fabricating a waveguide comprises: measuring misplacement of a photonic device relative to a substrate; generating computer readable instructions for using a plurality of graphics primitives to form the waveguide; and photocomposing the waveguide on the substrate in accordance with the computer readable instructions. A reticle comprises a plurality of graphics primitives with at least one of the plurality of graphics primitives comprising a tapered end. A waveguide comprises a plurality of waveguide segments with each of the plurality of waveguide segments comprising a tapered end and being adjacent to at least one other of the plurality of waveguide segments.