Leilei Living Song

US Patent:

7089485, Aug 8, 2006

Filed:

Feb 2, 2001

Appl. No.:

09/776175

Inventors:

Kamran Azadet - Morganville NJ, US
Leilei Song - Eatontown NJ, US
Thomas E. Truman - Red Bank NJ, US
Meng-Lin Yu - Morganville NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 11/00

US Classification:

714798, 714799, 714775, 714789, 370503, 375357

Abstract:

A data structure, method and protocol wherein synchronization data indicative of a data frame delineation point is inserted within an inter-packet gap (IPG) proximate a data frame during transmission. Optionally, a cyclical redundancy check (CRC) length indicative data, pointer data, and other data is inserted within the IPG to further insure appropriate delineation of data frames within a data stream.

US Patent:

7117425, Oct 3, 2006

Filed:

Sep 23, 2002

Appl. No.:

10/251776

Inventors:

Lisa Fredrickson - Long Beach CA, US
Leilei Song - Red Bank NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03M 13/00

US Classification:

714785

Abstract:

A Reed Solomon decoder architecture that uses a modified version of the error-evaluator polynomial form having a significantly reduced area of the dominant PDU unit, without loss in iteration time, in slice circuitry, which rotates terms to share a common multiplier and other circuitry. In addition, a B polynomial is stored, and associated overflow flags are implemented, to allow its storage to be minimized using a dual-multiplier arrangement. The decoder for error correcting codes comprises a syndrome calculation circuit, and a polynomial determining unit comprising slices, and a single multiplier in each of the slices, wherein each of the slices is employed a plurality of times in successive clock cycles. A correction circuit comprises a first multiplier employed when a scratch polynomial has overflowed, and a second multiplier employed when not overflowed.

US Patent:

7254771, Aug 7, 2007

Filed:

May 23, 2000

Appl. No.:

09/577177

Inventors:

Leilei Song - Eatontown NJ, US
Meng-Lin Yu - Morganville NJ, US

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H03M 13/00

US Classification:

714781, 714794

Abstract:

A method of decoding interleaved Reed-Solomon codes to achieve an improved performance for burst errors is described. The method takes advantage of both interleaving and erasure decoding to increase the error correcting capability of a system without necessarily depending on channel reliability information. The observed correlation of burst errors in interleaved systems is advantageously used to achieve an improved error-correcting system, wherein a first code word is decoded, and the error locations in the first codeword are used to determine erasures for the remaining code words in the same interleaving block, and finally, decoding the remaining code words in parallel.

US Patent:

7509564, Mar 24, 2009

Filed:

May 13, 2005

Appl. No.:

11/129193

Inventors:

Ralf Dohmen - Nuremberg, DE
Timo Frithjof Schuering - Nuremberg, DE
Leilei Song - Eatontown NJ, US
Meng-Lin Mark Yu - Morganville NJ, US

Assignee:

Agere Systems Inc. - Allentown PA
Alcatel-Lucent USA Inc. - Murray Hill NJ

International Classification:

H03M 13/00

US Classification:

714782, 714784, 714757

Abstract:

A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

US Patent:

7610495, Oct 27, 2009

Filed:

Jun 23, 2004

Appl. No.:

10/874834

Inventors:

Kameran Azadet - Morganville NJ, US
Leilei Song - Eatontown NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 1/00
G06F 1/26
G06F 1/32

US Classification:

713300, 713320, 4551271, 4551275, 455522, 455574

Abstract:

A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A disclosed power management process monitors the battery level of an electronic device and selects a transmission mode (e. g. , a transmission rate) with a lower power consumption when the battery power level reaches one or more predefined threshold levels.

US Patent:

7813436, Oct 12, 2010

Filed:

Sep 6, 2007

Appl. No.:

11/851115

Inventors:

Qing Zhao - Santa Clara CA, US
Jungwon Lee - Cupertino CA, US
Leilei Song - Sunnyvale CA, US
Songping Wu - Sunnyvale CA, US
Hui-Ling Lou - Palo Alto CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H04K 1/10
H04L 27/28

US Classification:

375260, 375216, 375345, 4551271, 4552321

Abstract:

In a method for synchronizing a receiver to a synchronous signal, a plurality of potential symbols are detected in a signal, the signal having been processed based on automatic gain control (AGC) with a varying gain. Next frame potential symbols corresponding to potential symbols in the plurality of potential symbols are determined, the next frame potential symbols being in frames subsequent to the frames in which the corresponding potential symbols are located. A gain of the AGC is fixed for each corresponding symbol interval during which a next frame potential symbol is operated on by the AGC. In between next frame potential symbols, the AGC is allowed to vary. Next frame potential symbols are analyzed after a transform is calculated to determine if any correspond to a start of a frame.

US Patent:

8019023, Sep 13, 2011

Filed:

Aug 15, 2007

Appl. No.:

11/839004

Inventors:

Leilei Song - Sunnyvale CA, US
Jungwon Lee - Cupertino CA, US
Woong Jun Jang - Stanford CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H04L 27/06

US Classification:

375340

Abstract:

Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where a receiver has received one or more signal vectors from the same transmitted vector. The receiver processes these received signal vectors one by one, and uses information from signal vectors that have already been processed to process the next signal vector. To process a current signal vector, the receiver concatenates the current signal vector with a previously processed signal vector. This concatenated signal vector is decoded using, for example, a maximum-likelihood (ML). To decode the concatenated signal vector, the ML decoder can use a concatenated channel matrix that includes a channel response matrix associated with the current signal vector and a processed version of previous channel response matrices.

US Patent:

8027402, Sep 27, 2011

Filed:

Jul 20, 2007

Appl. No.:

11/781208

Inventors:

Jungwon Lee - Cupertino CA, US
Woong Jun Jang - Stanford CA, US
Leilei Song - Sunnyvale CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H04B 7/02

US Classification:

375267, 375347, 375299, 455101, 455132

Abstract:

Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The symbols of the received signal vectors are combined, forming a combined received signal vector that may be treated as a single received signal vector. The combined signal vector is then decoded using a maximum-likelihood decoder. In some embodiments, the combined received signal vector may be processed prior to decoding. Systems and methods are also provided for computing soft information from a combined signal vector based on a decoding metric. Computationally intensive calculations can be extracted from the critical path and implemented in preprocessors and/or postprocessors.