Lee Y Spall

US Patent:

6622199, Sep 16, 2003

Filed:

Jul 2, 1999

Appl. No.:

09/347244

Inventors:

Lee Young Spall - San Diego CA

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

G06F 1200

US Classification:

711103, 711166

Abstract:

A method for allocating blocks within sectored EEPROM (commonly referred to as flash memory) based memory to minimize data relocation overhead and maximize sectored EEPROM lifetime. Data to be saved within sectored EEPROM is configured into data pages or blocks representing the minimum data size that is relocated within the sectored EEPROM in any given erase cycle. Multiple data blocks are contained within a single sector. A sector represents the minimum data size that is erased from the sectored EEPROM in any single erase cycle. Each block has a corresponding calculated value of volatility and new or updated data blocks to be added to the file are saved in sectored EEPROM according to a hierarchy based upon the calculated volatility of the data block. Data blocks with a calculated volatility within a predetermined threshold of the average volatility of a sector are saved within the most occupied sector containing no obsolete blocks. If no such sector exists then the data block is saved in the first available empty sector.

US Patent:

62629131, Jul 17, 2001

Filed:

Oct 19, 1999

Appl. No.:

9/420890

Inventors:

James A. Hutchison - San Diego CA
Lee Spall - San Diego CA

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

G11C 1134

US Classification:

36518509

Abstract:

A method and apparatus for updating and storing a counter value. In response to each of a plurality of N counter update signals, a binary memory cell is selected from a plurality of binary memory cells and the state of the selected binary memory cell is inverted. After the N counter update signals are received, a register that is separate from the plurality of binary memory cells is incremented, and the process is then repeated in response to further counter update signals. Each of the plurality of binary memory cells is inverted on average an equal number of times during each repetition of the process. The states of the plurality of binary memory cells and the value in the register represent the counter value at any given time.