Lawrence F Wagner

Author:

Lawrence C. Wagner

ISBN #:

0412145618

US Patent:

20050216873, Sep 29, 2005

Filed:

Mar 23, 2004

Appl. No.:

10/807478

Inventors:

Raminderpal Singh - Essex Junction VT, US
Yue Tan - Poughkeepsie NY, US
Jean-Oliver Plouchart - New York NY, US
Lawrence Wagner - Fishkill NY, US
Mohamed Talbi - Poughkeepsie NY, US
John Safran - Wappingers Falls NY, US
Kun Wu - Poughkeepsie NY, US

International Classification:

G06F017/50

US Classification:

716005000, 716004000, 716008000

Abstract:

A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.

US Patent:

60235772, Feb 8, 2000

Filed:

Sep 26, 1997

Appl. No.:

8/938676

Inventors:

George E. Smith - Wappingers Falls NY
Lawrence F. Wagner - Fishkill NY
Timothy L. Walters - Poughkeepsie NY
Fariborz Assaderaghi - Mahopac NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06G 748

US Classification:

39550035

Abstract:

A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that, current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.

US Patent:

53410238, Aug 23, 1994

Filed:

Jun 18, 1992

Appl. No.:

7/900881

Inventors:

Chang-Ming Hsieh - Fishkill NY
Louis L. C. Hsu - Fishkill NY
Ronald W. Knepper - LaGrangeville NY
Lawrence F. Wagner - Fishkill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2972

US Classification:

257559

Abstract:

A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.

US Patent:

53710223, Dec 6, 1994

Filed:

Feb 28, 1994

Appl. No.:

8/203129

Inventors:

Chang-Ming Hsieh - Fishkill NY
Louis L. G. Hsu - Fishkill NY
Ronald W. Knepper - LaGrangeville NY
Lawrence F. Wagner - Fishkill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21265

US Classification:

437 32

Abstract:

A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.

US Patent:

61416320, Oct 31, 2000

Filed:

Sep 2, 1999

Appl. No.:

9/388594

Inventors:

George E. Smith - Wappingers Falls NY
Fariborz Assaderaghi - Mahopac NY
Paul D. Muench - Poughkeepsie NY
Lawrence F. Wagner - Fishkill NY
Timothy L. Walters - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06G 748

US Classification:

703 14

Abstract:

A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.

US Patent:

57708819, Jun 23, 1998

Filed:

Sep 12, 1996

Appl. No.:

8/712538

Inventors:

Mario M. A. Pelella - Poughkeepsie NY
Fariborz Assaderaghi - Mahopac NY
Lawrence Federick Wagner - Fishkill NY

Assignee:

International Business Machines Coproration - Armonk NY

International Classification:

H01L 2701

US Classification:

257347

Abstract:

Producing a gap between a source and/or drain region of a silicon-on-insulator (SOI) field effect transistor which is less than the thickness of a depletion region normally surrounding the source and/or drain region, preferably at zero volts bias, permits gain of a parasitic bipolar transistor formed therewith to be transiently reduced and the effective base-emitter junction capacitance to be transiently increased during only modes of operation in which the parasitic bipolar conduction dominates normal operation of the field effect transistor. Such transient reduction of gain coupled with a transient reduction of high frequency response reduces the parasitic bipolar current spike to a degree greater than previously achievable and is fully compatible with other techniques of reducing such current spike. As applied to an SOICMOS SRAM, the transistor structure including such a gap is effective in suppressing half-select write disturb effects while maintaining the benefits of excess charge storage and floating body effects in the transistor.

US Patent:

54463122, Aug 29, 1995

Filed:

Jun 24, 1994

Appl. No.:

8/264885

Inventors:

Chang-Ming Hsieh - Fishkill NY
Louis L. G. Hsu - Fishkill NY
Ronald W. Knepper - LaGrangeville NY
Lawrence F. Wagner - Fishkill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2970

US Classification:

257559

Abstract:

A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.

US Patent:

52586405, Nov 2, 1993

Filed:

Sep 2, 1992

Appl. No.:

7/939214

Inventors:

Chang-Ming Hsieh - Fishkill NY
Louis L. Hsu - Fishkill NY
Phung T. Nguyen - Poughkeepsie NY
Lawrence F. Wagner - Fishkill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2948
H01L 2956

US Classification:

257471

Abstract:

An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.