Krzysztof Dobecki

US Patent:

7107424, Sep 12, 2006

Filed:

Mar 25, 2004

Appl. No.:

10/809733

Inventors:

Armen D. Avakian - Natick MA, US
Adam C. Peltz - Grafton MA, US
Krzysztof Dobecki - Framingham MA, US
Gregory S. Robidoux - Westboro MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 13/00
G06F 13/43
G11C 7/00
G06F 1/04
G06F 1/06
G06F 1/08

US Classification:

711167, 711168, 711169, 713400, 713401, 713500, 713503, 365193, 365194

Abstract:

A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.

US Patent:

7178000, Feb 13, 2007

Filed:

Mar 18, 2004

Appl. No.:

10/803377

Inventors:

Krzysztof Dobecki - Framingham MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 12/00

US Classification:

711168, 711149, 711131

Abstract:

A system for storing and retrieving data provided by the system on a system bus in a sequence at a predetermined system data rate. The system includes a system memory controller for enabling a system memory to store and retrieve the data at a rate twice the system data rate. Also provided is a trace buffer having a dual port random access memory. A trace buffer control system is provided for enabling the data on the system bus and fed concurrently to a pair of data ports of the dual port random access memory to be stored in the dual port random access memory at the predetermined system data rate and for enabling such dual port random access memory stored data to be retrieved from the dual port random access memory in the same sequence as such data was provided on the system data bus.

US Patent:

7383492, Jun 3, 2008

Filed:

Mar 20, 2003

Appl. No.:

10/392626

Inventors:

Philip M. Sailer - Needham MA, US
Nicholas Paluzzi - Hopkinton MA, US
Avinash Kallat - Marlborough MA, US
Stephen L. Scaringella - Holliston MA, US
Krzysztof Dobecki - Framingham MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 11/00
H03M 13/00
G11C 29/00

US Classification:

714801, 714776, 714719

Abstract:

A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker. In another embodiment, the generator is a frame delimiter generator and the checker is a frame delimiter checker.

US Patent:

6611879, Aug 26, 2003

Filed:

Apr 28, 2000

Appl. No.:

09/561161

Inventors:

Krzysztof Dobecki - Framingham MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1300

US Classification:

710 1, 710 4, 710 7, 710 20, 710 21, 710 33, 710 36, 710 46, 710 52

Abstract:

A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.