Kristopher J Kopel

US Patent:

20080270854, Oct 30, 2008

Filed:

Apr 24, 2007

Appl. No.:

11/739599

Inventors:

Kristopher Kopel - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G11C 29/52

US Classification:

714719

Abstract:

A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs fail information for at least a part of the memory device. The queue stores the fail information. The redundancy analyzer processes the fails using the fail information and produces a plurality of repair solutions. The types of fails include must fails and sparse fails. The fail information is transmitted to the queue, and the fail information includes at least a part of the fail information for the entire memory device. The tester can operate asynchronously from the redundancy analyzer.

US Patent:

20090265588, Oct 22, 2009

Filed:

Jun 24, 2009

Appl. No.:

12/490657

Inventors:

Kristopher Kopel - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 29/00
G06F 11/16

US Classification:

714710, 714E11054

Abstract:

A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs fail information for at least a part of the memory device. The queue stores the fail information. The redundancy analyzer processes the fails using the fail information and produces a plurality of repair solutions. The types of fails include must fails and sparse fails. The fail information is transmitted to the queue, and the fail information includes at least a part of the fail information for the entire memory device. The tester can operate asynchronously from the redundancy analyzer.

US Patent:

20230111510, Apr 13, 2023

Filed:

Dec 6, 2022

Appl. No.:

18/075958

Inventors:

- Boise ID, US
Lu Tong - Singapore, SG
Kristopher Kopel - Boise ID, US
Chang H. Siau - Saratoga CA, US

International Classification:

G06F 11/20
G11C 16/04
G11C 16/26

Abstract:

Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).