Kevin Allen Whitehill

US Patent:

6506652, Jan 14, 2003

Filed:

Dec 9, 1999

Appl. No.:

09/458357

Inventors:

Chia-Hong Jan - Portland OR
Julie A. Tsai - Beaverton OR
Simon Yang - Portland OR
Tahir Ghani - Beaverton OR
Kevin A. Whitehill - Portland OR
Steven J. Keating - Beaverton OR
Alan Myers - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21336

US Classification:

438303, 438595, 438649, 438655

Abstract:

A method and device for improved salicide resistance in polysilicon gates under 0. 20 m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks.

US Patent:

6509618, Jan 21, 2003

Filed:

Jan 4, 2000

Appl. No.:

09/476920

Inventors:

Chia-Hong Jan - Portland OR
Julie A. Tsai - Beaverton OR
Simon Yang - Portland OR
Tahir Ghani - Beaverton OR
Kevin A. Whitehill - Portland OR
Steven J. Keating - Beaverton OR
Alan Myers - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2976

US Classification:

257413, 257900

Abstract:

A method and device for improved salicide resistance in polysilicon gates under 0. 20 m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks.

US Patent:

6521964, Feb 18, 2003

Filed:

Aug 30, 1999

Appl. No.:

09/386495

Inventors:

Chia-Hong Jan - Portland OR
Julie A. Tsai - Beaverton OR
Simon Yang - Portland OR
Tahir Ghani - Beaverton OR
Kevin A. Whitehill - Portland OR
Steven J. Keating - Beaverton OR
Alan Myers - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2976

US Classification:

257413, 257900

Abstract:

A method and device for improved salicide resistance in polysilicon gates under 0. 20 m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks.

US Patent:

6593633, Jul 15, 2003

Filed:

Jan 5, 2000

Appl. No.:

09/477869

Inventors:

Chia-Hong Jan - Portland OR
Julie A. Tsai - Beaverton OR
Simon Yang - Portland OR
Tahir Ghani - Beaverton OR
Kevin A. Whitehill - Portland OR
Steven J. Keating - Beaverton OR
Alan Myers - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2976

US Classification:

257389, 257384

Abstract:

The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

US Patent:

6777760, Aug 17, 2004

Filed:

Jan 5, 2000

Appl. No.:

09/477870

Inventors:

Chia-Hong Jan - Portland OR
Julie A. Tsai - Beaverton OR
Simon Yang - Portland OR
Tahir Ghani - Beaverton OR
Kevin A. Whitehill - Portland OR
Steven J Keating - Beaverton OR
Alan Myers - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2994

US Classification:

257384, 257383

Abstract:

A method and device for improved salicide resistance in polysilicon gates under 0. 20 m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks.

US Patent:

7211872, May 1, 2007

Filed:

Jan 4, 2000

Appl. No.:

09/477764

Inventors:

Chia-Hong Jan - Portland OR, US
Julie A. Tsai - Beaverton OR, US
Simon Yang - Portland OR, US
Tahir Ghani - Beaverton OR, US
Kevin A. Whitehill - Portland OR, US
Steven J. Keating - Beaverton OR, US
Alan Myers - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/76

US Classification:

257413, 257900

Abstract:

A method and device for improved salicide resistance in polysilicon gates under 0. 20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack within inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks.

US Patent:

62682547, Jul 31, 2001

Filed:

Dec 9, 1999

Appl. No.:

9/458538

Inventors:

Chia-Hong Jan - Portland OR
Julie A. Tsai - Beaverton OR
Simon Yang - Portland OR
Tahir Ghani - Beaverton OR
Kevin A. Whitehill - Portland OR
Steven J. Keating - Beaverton OR
Alan Myers - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21336

US Classification:

438303

Abstract:

A method and device for improved salicide resistance in polysilicon gates under 0. 20. mu. m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks.

US Patent:

61881171, Feb 13, 2001

Filed:

Mar 25, 1999

Appl. No.:

9/276477

Inventors:

Chia-Hong Jan - Portland OR
Julie A. Tsai - Beaverton OR
Simon Yang - Portland OR
Tahir Ghani - Beaverton OR
Kevin A. Whitehill - Portland OR
Steven J. Keating - Beaverton OR
Alan Myers - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 3300
H01L 2978

US Classification:

257413

Abstract:

A method and device for improved polycide resistance in polysilicon gates under 0. 20. mu. m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks.