Kevin T Jennings

US Patent:

6360295, Mar 19, 2002

Filed:

Sep 28, 1999

Appl. No.:

09/406974

Inventors:

Kevin F. Jennings - Novi MI

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1202

US Classification:

711105

Abstract:

A serial load controller and method for loading at least one input data bit serially into a memory. The memory is interfaced to a data bus and an address bus. The serial load controller includes a counter generating an internal address pointer signal in response to a first control signal. The first control signal indicates that the input data bit is to be transferred serially into the memory. The counter is responsive to the first control signal to reset the internal address pointer to an initial value. A multiplexer is coupled to select one of the address bus and the internal address pointer signal as an output address bus in response to the first control signal. Suitable transceivers or other bus drivers are provided for driving at least a first input data bit onto the data bus in response to the clock pulse.

US Patent:

20070255874, Nov 1, 2007

Filed:

Apr 20, 2007

Appl. No.:

11/788724

Inventors:

Kevin F. Jennings - Novi MI, US

International Classification:

G06F 13/00
G06F 13/36

US Classification:

710113, 710110

Abstract:

A system and method for slave-side arbitration includes a plurality of master devices, a target device, and an arbitrator for arbitrating access to the target device by the master devices. Queuing devices, such as FIFO buffers, are respectively associated with master devices and communicate information regarding retained target device access requests to the arbitrator. The information may be communicated to the arbitrator by sending it to the arbitrator, or may be provided as status information that is accessed by the arbitrator. The arbitrator uses an arbitration scheme and information regarding retained transaction requests to determine which master device should be granted access to the target device. The arbitration system and method can be used in an integrated circuit with multiple embedded processors, and can be implemented in a document processing system to improve overall system performance over conventional slave-side arbitration schemes.

US Patent:

56340605, May 27, 1997

Filed:

Aug 9, 1994

Appl. No.:

8/287878

Inventors:

Kevin F. Jennings - Novi MI

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 13362

US Classification:

395729

Abstract:

An apparatus for and method of granting access to a shared resource wherein the shared resource is accessed by a plurality of users. In a first exemplary embodiment of the present invention, a priority controller can assign priority to a number of users based upon the combination of shared resource request signals received by the priority controller. For each combination of shared resource request signals, a different priority may be assigned to each user by the priority controller. In another exemplary embodiment of the present invention, each user may supply additional information bits to the priority controller to indicate a "requested priority" for a the shared resource. The priority controller then weighs the priority requests from each user, including the additional information bits, and determines an optimum priority assignment. That is, the users themselves may influence the priority assigned thereto by providing the additional information bits to the priority controller.

US Patent:

61697036, Jan 2, 2001

Filed:

May 21, 1997

Appl. No.:

8/861274

Inventors:

Kevin F. Jennings - Novi MI

Assignee:

Unisys Corp. - Blue Bell PA

International Classification:

G11C 800
G11C 700

US Classification:

365233

Abstract:

A method for controlling a high speed memory unit M to be read from, and written to, as initiated by clock signals of comparable speed, this method involving: providing a timing coordinator unit with bi-stable store for storing and presenting certain input signals to the memory unit in conjunction with the clock signals so as to be immediately useable thereby and so that the memory unit can responsively output data to a user stage; these input signals being arranged to include commands R/W to Read or Write, Address signals and Data signals; and the memory unit being maintained in "ready-to-read" condition at all times except during receipt of write commands.

US Patent:

55175848, May 14, 1996

Filed:

Aug 9, 1994

Appl. No.:

8/287879

Inventors:

Kevin F. Jennings - Novi MI

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06K 936

US Classification:

382276

Abstract:

An image processing hardware element that may be used to implement any number of data manipulation methods. The hardware element may be dedicated to the selected manipulation method such that maximum performance may be attained. The hardware element may be programmed to implement a particular manipulation method by simply down loading new values into the hardware element.

US Patent:

53053982, Apr 19, 1994

Filed:

Oct 10, 1989

Appl. No.:

7/420779

Inventors:

Robert Klein - Farmington MI
Audrey A. Brennan - Northville MI
Kevin Jennings - Farmington Hills MI

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06K 942

US Classification:

382 47

Abstract:

An application specific integrated circuit (ASIC) provides sufficient information about the size of the image, as well as pixel data, to permit a scaling processor to change the size of the image for further processing.

US Patent:

61483850, Nov 14, 2000

Filed:

May 21, 1997

Appl. No.:

8/861273

Inventors:

Kevin F. Jennings - Novi MI

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1200

US Classification:

711167

Abstract:

The invention includes apparatus for controlling a high speed memory unit M that is written to on every cycle and read from on every cycle except during receipt of write commands. The apparatus includes a timing coordinator with bi-stable storage means that store and present certain signals to the memory in conjunction with clock signals so as to be immediately usable by the memory, and so that the memory can responsively output data to a user. The signals include commands R/W to Read or Write, Address signals and Data signals.

US Patent:

50071009, Apr 9, 1991

Filed:

Oct 10, 1989

Appl. No.:

7/419606

Inventors:

Robert D'Aoust - Detroit MI
Robert B. Cording - Livonia MI
Debora Y. Grosse - Ann Arbor MI
Kevin Jennings - Farmington Hills MI
Stephen R. Krebs - Ypsilanti Township, Washtenaw County MI
George E. Reasoner - Tecumseh MI
Gerald R. Smith - Farmington MI
David C. Williams - Ann Arbor MI

Assignee:

Unisys Corporation - Bluebell PA

International Classification:

G06K 954

US Classification:

382 49

Abstract:

A pipelined image processor is disclosed which contains a diagnostic apparatus which, under normal processing conditions, is coupled to and is in communication with resequencer, image processor, and transposer/compressor assemblies contained within the pipelined image processor. The diagnostic apparatus of this invention causes a diagnostic test pattern to be sent to the re-sequencer and image processor entities of the pipelined image processor and monitors the response thereof. This response is then used to detect faults which have occurred in these entities.