Kenneth Roberts Zin

US Patent:

7978105, Jul 12, 2011

Filed:

Jan 8, 2010

Appl. No.:

12/684773

Inventors:

Kenneth Thet Zin Oo - Milpitas CA, US
Pierte Roo - Sunnyvale CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 1/10

US Classification:

341120, 341155

Abstract:

In one embodiment, a first resistor ladder includes a first voltage across the first resistor ladder. A second resistor ladder includes a second voltage across the second resistor ladder. A third resistor ladder includes a third voltage across the third resistor ladder. The calibrator receives the first voltage and third voltage and adjusts a current through the third resistor ladder to adjust the third voltage based on the received first voltage and third voltage. A buffer is configured to provide buffering for the third resistor ladder from the second resistor ladder. The third voltage of the third resistor ladder is stable even though the second voltage of the second resistor ladder is changing.

US Patent:

8022765, Sep 20, 2011

Filed:

Sep 2, 2009

Appl. No.:

12/552882

Inventors:

Kenneth Thet Zin Oo - Milpitas CA, US
Pierte Roo - Sunnyvale CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03G 3/30

US Classification:

330285, 330136

Abstract:

Circuits and methods for compensating for an input-dependent gain error in a buffer and/or amplifier circuit, including applying a dynamic current to the input transistor. Circuits generally include a dynamic current supply coupled to a terminal of the input transistor, the dynamic current supply providing a compensating current. The compensating current can have a magnitude equal to the output impedance of the input transistor times a magnitude of the output voltage. The compensating current can be provided via a current mirror, or directly to a terminal of the input transistor. Methods generally include regulating variations in the current through the input transistor by sinking or sourcing a static current and a dynamic current at a terminal of the input transistor. The dynamic current can be regulated in response to a variation in the input signal.

US Patent:

8030974, Oct 4, 2011

Filed:

Sep 2, 2009

Appl. No.:

12/552684

Inventors:

Kenneth Thet Zin Oo - Milpitas CA, US

Assignee:

Marvell International, Ltd. - Hamilton

International Classification:

G11C 27/02
H03K 5/00
H03K 17/00

US Classification:

327 94

Abstract:

Aspects of the disclosure provide a sampling circuit having reduced sampling distortions. The sampling circuit can include a switch having a control terminal, a first channel terminal and a second channel terminal. The first channel terminal can be configured to receive an input signal, and the control terminal can be configured to have a control voltage that varies with regard to the input signal, such that a conducting channel can be formed between the first channel terminal and the second channel terminal to enable an output voltage on the second channel terminal to track the input signal. Further, the sampling circuit can include a bootstrap module coupled to the control terminal of the switch. The bootstrap module can be configured to change the control voltage by a substantially constant value to turn off the conducting channel between the first channel terminal and the second channel terminal in order to hold the output voltage as a sample of the input signal. In addition, the bootstrap module can be configured to couple a voltage increase to the control terminal of the switch to increase a turn-on speed of the switch.

US Patent:

8049652, Nov 1, 2011

Filed:

Jan 8, 2010

Appl. No.:

12/684760

Inventors:

Kenneth Thet Zin Oo - Milpitas CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 1/14

US Classification:

341156, 341158

Abstract:

A coarse reference ladder provides a plurality of coarse references. A coarse ADC receives an input voltage. The coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output. A switch matrix is configured to close a switch based on the coarse output. An input line corresponding to a coarse reference is coupled to the switch matrix. The input line is precharged to the input voltage. The input line settles from the precharged input voltage to the coarse reference. A fine reference ladder provides a plurality of fine references based on the coarse reference. A fine ADC receives the input voltage and performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output. Logic outputs a digital output for the input voltage based on the coarse output and the fine output.

US Patent:

8077069, Dec 13, 2011

Filed:

Jan 8, 2010

Appl. No.:

12/684735

Inventors:

Kenneth Thet Zin Oo - Milpitas CA, US
Pierte Roo - Sunnyvale CA, US
Xiong Liu - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H03M 1/14

US Classification:

341156, 341158

Abstract:

First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. In one embodiment, the coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output based on the first comparison. A switch matrix includes a plurality of switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides a plurality of fine references. A fine ADC performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.

US Patent:

8183890, May 22, 2012

Filed:

Sep 2, 2009

Appl. No.:

12/552543

Inventors:

Kenneth Thet Zin Oo - Milpitas CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11C 27/02
H03K 5/00
H03K 17/00

US Classification:

327 94, 327427

Abstract:

Aspects of the disclosure provide a sampling circuit with reduced sampling distortions. The sampling circuit can include a switch having a control terminal, a first channel terminal and a second channel terminal. Further, the sampling circuit can include a first driving module configured to receive an input signal and drive a first signal in response to the input signal onto the first channel terminal of the switch. In addition, the sampling circuit can include a bootstrap module coupled to the control terminal of the switch and a second driving module coupled to the bootstrap module. The second driving module can be configured to receive the input signal and drive a second signal in response to the input signal to the bootstrap module, such that the bootstrap module can vary a control voltage on the control terminal of the switch based on the input signal for turning on the switch in a track-mode and causing an output voltage on the second channel terminal of the switch to track the first signal on the first channel terminal of the switch.

US Patent:

8354865, Jan 15, 2013

Filed:

Sep 29, 2011

Appl. No.:

13/248659

Inventors:

Kenneth Thet Zin Oo - Milpitas CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11C 27/02
H03K 5/00
H03K 17/00

US Classification:

327 94

Abstract:

A sampling circuit can include a switch having a control terminal, a first channel terminal and a second channel terminal. The first channel terminal can be configured to receive an input signal, and the control terminal can be configured to have a control voltage that varies with regard to the input signal, such that a conducting channel can be formed between the first channel terminal and the second channel terminal to enable an output voltage on the second channel terminal to track the input signal. Further, the sampling circuit can include a bootstrap module coupled to the control terminal of the switch. The bootstrap module can be configured to change the control voltage by a substantially constant value to turn off the conducting channel between the first channel terminal and the second channel terminal in order to hold the output voltage as a sample of the input signal.

US Patent:

8581635, Nov 12, 2013

Filed:

Jan 14, 2013

Appl. No.:

13/740576

Inventors:

- Hamilton, BM
Kenneth Thet Zin Oo - Milpitas CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11C 27/02
H03K 5/00
H03K 17/00

US Classification:

327 94

Abstract:

Aspects of the disclosure provide a sampling circuit having reduced sampling distortions. The sampling circuit can include a switch having a control terminal, a first channel terminal and a second channel terminal. The first channel terminal can be configured to receive an input signal, and the control terminal can be configured to have a control voltage that varies with regard to the input signal, such that a conducting channel can be formed between the first channel terminal and the second channel terminal to enable an output voltage on the second channel terminal to track the input signal. Further, the sampling circuit can include a bootstrap module coupled to the control terminal of the switch. The bootstrap module can be configured to change the control voltage by a substantially constant value to turn off the conducting channel between the first channel terminal and the second channel terminal in order to hold the output voltage as a sample of the input signal. In addition, the bootstrap module can be configured to couple a voltage increase to the control terminal of the switch to increase a turn-on speed of the switch.