Kenneth L Wright

US Patent:

20060058658, Mar 16, 2006

Filed:

Sep 13, 2004

Appl. No.:

10/940236

Inventors:

Ricky King - Sunnyvale CA, US
Kenneth Wright - San Jose CA, US

International Classification:

A61B 8/00

US Classification:

600437000

Abstract:

Two different operating systems, such as one using Windows real-time extensions and another using Windows NT or other non-real-time operating system, may be implemented on a same system or hardware, such as being co-located on a same processor, without changing client software. Two or more software processes are run on a same processor or system. The software or operating systems communicate using a socket application programming interface. The use of socket communications allows the processes to communicate as if the processes were on different systems. Socket communications between the two operating systems are intercepted by the layered service provider before being provided to the hardware for external transport. The socket communications are re-routed to the socket stack of the destination operating system. The socket communication using sockets is transparent to the application or middleware layer software. By providing for socket communications between two co-located operating systems, the implementation cost and development risk caused by using a shared memory may be avoided.

US Patent:

20220406354, Dec 22, 2022

Filed:

Jun 28, 2022

Appl. No.:

17/852266

Inventors:

- San Jose CA, US
John Eric Linstadt - Palo Alto CA, US
Kenneth L. Wright - Sunnyvale CA, US

International Classification:

G11C 11/00
G06F 12/0804
G06F 12/084
G06F 12/0895
G11C 5/04
G11C 14/00
G06F 12/02

Abstract:

A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

US Patent:

20220382691, Dec 1, 2022

Filed:

Jun 2, 2022

Appl. No.:

17/830838

Inventors:

- San Jose CA, US
John Eric Linstadt - Palo Alto CA, US
Kenneth Lee Wright - Sunnyvale CA, US

International Classification:

G06F 13/16
G06F 13/28

Abstract:

A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

US Patent:

20220350763, Nov 3, 2022

Filed:

May 19, 2022

Appl. No.:

17/748762

Inventors:

- San Jose CA, US
Ely Tsern - Los Altos CA, US
John Eric Linstadt - Palo Alto CA, US
Thomas J. Giovannini - San Jose CA, US
Kenneth L. Wright - Sunnyvale CA, US

International Classification:

G06F 13/28
G11C 5/04
G11C 7/10
G06F 13/16

Abstract:

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

US Patent:

20220319578, Oct 6, 2022

Filed:

Apr 7, 2022

Appl. No.:

17/715370

Inventors:

- San Jose CA, US
John Eric Linstadt - Palo Alto CA, US
Zhichao Lu - San Jose CA, US
Kenneth Lee Wright - Sunnyvale CA, US

International Classification:

G11C 11/4091
G06F 11/10
G11C 11/4076

Abstract:

Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

US Patent:

20220300439, Sep 22, 2022

Filed:

Apr 7, 2022

Appl. No.:

17/715379

Inventors:

- San Jose CA, US
Kenneth L. Wright - Sunnyvale CA, US

International Classification:

G06F 13/16
G06F 11/07
G06F 13/40
G06F 11/20
G06F 11/16
G06F 11/10

Abstract:

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

US Patent:

20210134344, May 6, 2021

Filed:

Nov 16, 2020

Appl. No.:

17/099413

Inventors:

- San Jose CA, US
John Eric Linstadt - Palo Alto CA, US
Brent Steven Haukness - Sunnyvale CA, US
Kenneth L. Wright - Sunnyvale CA, US
Thomas Vogelsang - Mountain View CA, US

International Classification:

G11C 11/403
G11C 11/4097
G11C 11/4096
G11C 8/08
G11C 7/10
G11C 7/18
G11C 5/02
G11C 11/408
G06F 12/06
G11C 11/406
G11C 11/409

Abstract:

A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

US Patent:

20210118480, Apr 22, 2021

Filed:

Nov 5, 2020

Appl. No.:

17/089899

Inventors:

- San Jose CA, US
John Eric Linstadt - Palo Alto CA, US
Kenneth L. Wright - Sunnyvale CA, US

International Classification:

G11C 11/00
G06F 12/0804
G06F 12/084
G06F 12/0895
G11C 5/04
G11C 14/00
G06F 12/02

Abstract:

A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

Author:

Kenneth Wright

ISBN #:

0205319270

Author:

Kenneth Wright

ISBN #:

0439672724

Author:

Kenneth Wright

ISBN #:

0815194366

Author:

Kenneth Wright

ISBN #:

0876685599

Author:

Kenneth W. Wright

ISBN #:

0323001815

Author:

Kenneth W. Wright

ISBN #:

0387279245

Author:

Kenneth W. Wright

ISBN #:

0387279296

Author:

Kenneth W. Wright

ISBN #:

0387279326