Kenneth Michael Key

Address:

1009 Fls Brg Dr, Raleigh, NC 27614

Phone:

919 676-7043

VIN:

4JGDA5HB3CA027849

Make:

MERCEDES-BENZ

Model:

M-CLASS

Year:

2012

US Patent:

6356548, Mar 12, 2002

Filed:

Jun 29, 1998

Appl. No.:

09/106245

Inventors:

Scott Nellenbach - Apex NC
Kenneth Michael Key - Raleigh NC
Edward D. Paradise - Chapel Hill NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 1240

US Classification:

370362, 370462, 370401

Abstract:

A multi-port switching device architecture decouples decode logic circuitry of each port of a network switch from its respective state machine logic circuitry and organizes the state machine logic as pools of transmit/receive engine resources that are shared by each of the decode logic circuits. Intermediate priority logic of the switching device cooperates with the decode logic and pooled resources to allocate frames among available resources in accordance with predetermined ordering and fairness policies. These policies prevent misordering of frames from a single source while ensuring that all ports in the device are serviced fairly.

US Patent:

6385747, May 7, 2002

Filed:

Dec 14, 1998

Appl. No.:

09/212314

Inventors:

Jeffery Burl Scott - Durham NC
Kenneth Michael Key - Raleigh NC
Michael L. Wright - Raleigh NC
Scott Nellenbach - Apex NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G11C 2900

US Classification:

714724, 365201

Abstract:

A technique is provided for use in testing replicated components (e. g. , identical circuit components) of an electronic device for defects. In one aspect of this testing technique, the same test inputs may be broadcast, in parallel, from a single test interface to each of the replicated components of the electronic device under test. Respective test outputs generated by the replicated components in response to the test inputs may be supplied to a comparator, comprised in the electronic device, that compares the respective test outputs to each other and generates a fault signal if corresponding test outputs are not identical. This fault signal may be supplied to an external test interface pin of the single test interface, and its assertion may indicate that one or more of the replicated components may be defective. The respective test outputs may be multiplexed to permit output via an external interface of respective test outputs from a selected component. These respective test outputs may be compared to expected values therefor whereby to determine presence and/or nature of defects in the replicated components.

US Patent:

6442669, Aug 27, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/727068

Inventors:

Michael L. Wright - Raleigh NC
Darren Kerr - Palo Alto CA
Kenneth Michael Key - Raleigh NC
William E. Jennings - Cary NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1500

US Classification:

712 19, 710 52

Abstract:

A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient âcontextâ data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

US Patent:

6513108, Jan 28, 2003

Filed:

Jun 29, 1998

Appl. No.:

09/106478

Inventors:

Darren Kerr - Palo Alto CA
Kenneth Michael Key - Raleigh NC
Michael L. Wright - Raleigh NC
William E. Jennings - Cary NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1516

US Classification:

712 19, 712 21

Abstract:

A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.

US Patent:

6681341, Jan 20, 2004

Filed:

Nov 3, 1999

Appl. No.:

09/432526

Inventors:

William Fredenburg - Apex NC
Kenneth Michael Key - Raleigh NC
Michael L. Wright - Raleigh NC
John William Marshall - Cary NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1100

US Classification:

714 30, 714 10, 714 11, 712 10, 712 11, 712 15

Abstract:

A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.

US Patent:

6836838, Dec 28, 2004

Filed:

Aug 16, 2002

Appl. No.:

10/222277

Inventors:

Michael L. Wright - Raleigh NC
Darren Kerr - Palo Alto CA
Kenneth Michael Key - Raleigh NC
William E. Jennings - Cary NC

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1500

US Classification:

712 19, 710 52

Abstract:

A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient âcontextâ data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

US Patent:

6851028, Feb 1, 2005

Filed:

Dec 28, 2001

Appl. No.:

10/035609

Inventors:

Kwok Ken Mak - Chapel Hill NC, US
Kenneth M. Key - Raleigh NC, US
Xiaoming Sun - Chapel Hill NC, US
L. Duane Richardson - Apex NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

711154, 711100, 709200

Abstract:

The present invention incorporates a technique that enables the processing of memory requests without requiring memory devices that support a request identifier (ID). The present invention maintains an association between a request identifier and a first memory request issued by a requestor and directed to a memory location. The first memory request contains an address corresponding to the memory location. A memory device corresponding to the address is selected. A second memory request without the identifier is issued to the selected memory device to access information stored at the location. The information is received from the memory device and associated with the request identifier.

US Patent:

6876961, Apr 5, 2005

Filed:

Aug 27, 1999

Appl. No.:

09/384504

Inventors:

John W. Marshall - Cary NC, US
Kenneth Michael Key - Raleigh NC, US
Scott Nellenbach - Apex NC, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F017/50

US Classification:

703 19, 703 2, 703 13, 703 22, 716 6, 716 7, 716 8

Abstract:

A technique is provided for use in computerized modeling of an electronic system. The technique bases simulation of the system's operation (e. g. , timing operation) upon both actual physical characteristics of a part of the system, and hierarchical analysis-based models of the rest of the system.