Kenneth C Creta

US Patent:

6681292, Jan 20, 2004

Filed:

Aug 27, 2001

Appl. No.:

09/940835

Inventors:

Kenneth C. Creta - Gig Harbor WA
Mike Bell - Beaverton OR
Robert George - Austin TX
Bradford B Congdon - Olympia WA
Robert Blankenship - Tacoma WA
Duane January - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

711119, 711141, 711145, 711146, 709217

Abstract:

A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.

US Patent:

6694383, Feb 17, 2004

Filed:

Dec 6, 2001

Appl. No.:

10/008595

Inventors:

Thai Q. Nguyen - Columbia SC
Robert J. Miller - Irmo SC
Kenneth C. Creta - Gig Harbor WA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 300

US Classification:

710 6, 710 5, 710 7

Abstract:

A first component that stores information about requests for information directed to an interface (e. g. , a bus of a computer system connected to components), receives an indication of a request sent by a second component to the interface. The first component sends an identifier for a subsequent request to the second component.

US Patent:

6801976, Oct 5, 2004

Filed:

Aug 27, 2001

Appl. No.:

09/940292

Inventors:

Kenneth C. Creta - Gig Harbor WA
Bradford B. Congdon - Olympia WA
Tony S Rand - Tacoma WA
Deepak Ramachandran - Tacoma WA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710310, 710 39, 710313

Abstract:

An input/output hub includes an inbound ordering queue (IOQ) to receive inbound transactions. All read and write transactions have a transaction completion. Peer-to-peer transactions are not permitted to reach a destination until after all prior writes in the IOQ have been completed. A write in a peer-to-peer transaction does not permit subsequent accesses to proceed until the write is guaranteed to be in an ordered domain of the destination. An IOQ read bypass buffer is provided to receive read transactions pushed from the IOQ to permit posted writes and read/write completions to progress through the IOQ. An outbound ordering queue (OOQ) stores outbound transactions and completions of the inbound transactions. The OOQ also issues write completions for posted writes. An OOQ read bypass buffer is provided to receive read transactions pushed from the OOQ to permit posted writes and read/write completions to progress through the OOQ.

US Patent:

6859864, Feb 22, 2005

Filed:

Dec 29, 2000

Appl. No.:

09/752576

Inventors:

Manoj Khare - Saratoga CA, US
Lily P. Looi - Portland OR, US
Akhilesh Kumar - Sunnyvale CA, US
Kenneth C. Creta - Gig Harbor WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711146, 711121, 711141

Abstract:

A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read request to a snoop based architecture controller switch. The switch recognizes that another node other than the requesting node and the home node for the desired data has a copy of the data. The switch directs the request to the responding node that is not the home node. The responding node, having modified the data, provides a single response back to the switch that causes the switch to both update the data at the home node and answer the requesting node. The updating of the data at the home node is done without receiving an explicit write instruction from the requesting node.

US Patent:

6915365, Jul 5, 2005

Filed:

Mar 22, 2002

Appl. No.:

10/104814

Inventors:

Kenneth C. Creta - Gig Harbor WA, US
Doug Moran - Folsom CA, US
Vasudevan Shanmugasundaram - Tumwater WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F013/00
G06F003/00
G06F013/36

US Classification:

710104, 710 10, 710314

Abstract:

Methods and apparatus for inbound PCI configuration cycles are disclosed. By definition, PCI bridges block upstream progress of configuration cycles initiated by a PCI bus master on their secondary buses. In the described embodiments, a PCI bus master can execute a configuration cycle despite this limitation, by converting the configuration cycle command to Memory Read and Write commands that a PCI bridge will forward upstream. The PCI bus master writes the address of a target configuration register to a first predefined address, and pushes or pulls data from that target register by subsequently initiating a memory access to a second predefined address. A platform chipset is designed to recognize Memory Read and Write accesses to the predefined addresses as relating to an inbound configuration cycle. When a memory access to the second address is received, the chipset uses the information stored at the first address to form and execute a configuration cycle on behalf of the downstream PCI bus master.

US Patent:

6976115, Dec 13, 2005

Filed:

Mar 28, 2002

Appl. No.:

10/112344

Inventors:

Kenneth Creta - Gig Harbor WA, US
Jasmin Ajanovic - Portland OR, US
Joseph Bennett - Roseville CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F013/36
G06F003/00

US Classification:

710310, 710 5, 710313, 711158

Abstract:

A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.

US Patent:

6976129, Dec 13, 2005

Filed:

Sep 30, 2002

Appl. No.:

10/261944

Inventors:

Kenneth C. Creta - Gig Harbor WA, US
Manoj Khare - Saratoga CA, US
Lily P. Looi - Portland OR, US
Akhilesh Kumar - Santa Clara CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711141, 711146, 711210, 707201

Abstract:

A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.

US Patent:

6978351, Dec 20, 2005

Filed:

Dec 30, 2002

Appl. No.:

10/335424

Inventors:

Randy B. Osborne - Beaverton OR, US
Kenneth C. Creta - Gig Harbor WA, US
Joseph A. Bennett - Roseville CA, US
Jasmin Ajanovic - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/08

US Classification:

711137, 711171

Abstract:

To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.