Kelvin E Mccollough

US Patent:

62294008, May 8, 2001

Filed:

Oct 22, 1999

Appl. No.:

9/426934

Inventors:

Kelvin E. McCollough - Austin TX
James John Caserta - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03D 309
H03L 708

US Classification:

331 17

Abstract:

In accordance with the present invention, a frequency modulating phase-locked-loop (FMPLL) (100) architecture is implemented. The frequency of the FMPLL (100) is controlled using a current controlled oscillator (ICO) (126). The ICO (126) receives a current signal incorporating feedback to maintain a fixed gain. The ICO (126) associated with the FMPLL (100) establishes a predictable change in the output frequency for a given change in its input controlled current (ICTL). Relying upon this fixed gain, a frequency shift can be created by summing in an additional delta current (IMOD) to the input control current. By periodically varying the magnitude of the current IMOD, a frequency modulated clock is produced at the output of the ICO 126. The magnitude of IMOD controls the amount of frequency shift of the frequency modulated clock. By providing an IMOD signal which is proportional to the generated system frequency, a frequency shift proportional to the average, or center, frequency is produced.

US Patent:

61608610, Dec 12, 2000

Filed:

Oct 22, 1999

Appl. No.:

9/425881

Inventors:

Kelvin E. McCollough - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03D 324

US Classification:

375376

Abstract:

In accordance with the present invention, a frequency modulating phase-locked-loop (FMPLL) (100) architecture is implemented. The frequency of the FMPLL (100) is controlled using a current controlled oscillator (ICO) (126). The ICO (126) receives a current signal incorporating feedback to maintain a fixed gain. The ICO (126) associated with the FMPLL (100) establishes a predictable change in the output frequency for a given change in its input controlled current (ICTL). Relying upon this fixed gain, a frequency shift can be created by summing in an additional delta current (IMOD) to the input control current. By periodically varying the magnitude of the current IMOD, a frequency modulated clock is produced at the output of the ICO 126. The magnitude of IMOD controls the amount of frequency shift of the frequency modulated clock. By providing an IMOD signal which is proportional to the generated system frequency, a frequency shift proportional to the average, or center, frequency is produced.

US Patent:

53592948, Oct 25, 1994

Filed:

Oct 5, 1993

Appl. No.:

8/132004

Inventors:

Jeffrey D. Ganger - Austin TX
Kelvin E. McCollough - Austin TX
Jules D. Campbell - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 345

US Classification:

330258

Abstract:

A charge-balanced switched-capacitor circuit (50, 61) includes two capacitors (53, 54/72, 73) which are equalized by being connected in parallel during a first time period. This equalization cancels any mismatch in either capacitor (53, 54/72, 73) which would tend to affect an associated common-mode voltage. During a second time period, the two capacitors (53, 54/72, 73) are connected in series between two signal lines (42, 43). In one embodiment, the switched-capacitor circuit (50) forms a common-mode feedback sensing circuit by providing a common-mode feedback voltage to a fully-differential amplifier (41) at a common interconnection point of the two capacitors (53, 54). This embodiment draws no DC current, and thus prevents harmonic distortion of an output signal on the two signal lines when using a slew-rate limited amplifier (41). In another embodiment, the switched-capacitor circuit (61) functions as an input sampler at an input of a switched-capacitor amplifier circuit (60).

US Patent:

61218499, Sep 19, 2000

Filed:

Jul 24, 1998

Appl. No.:

9/121700

Inventors:

Kelvin Edward McCollough - Austin TX
Boaz Kochman - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03B 500
H03L 300

US Classification:

331175

Abstract:

An integrated circuit (11) has a frequency detection circuit (22) which provides one or more digital signals (50) to a current source (26) based upon a detected frequency of operation of a generated reference clock (48). The signals (50) allows the current source (26) to change its operational state between two or more discrete current output levels in a digitally-controlled manner. Using signals (50), a high current output level can selected and provided by the current source (26) to the external oscillator circuit (16) during a start up mode to ensure that the integrated circuit (11) can start up in an optimally reduced time period. After a start up operation is complete, the signals (50) can then be used to switch the current source (26) into a lower current operational mode whereby electromagnetic interference (EMI) effects are reduced during the normal modes of operation occurring after start up.

US Patent:

52818675, Jan 25, 1994

Filed:

Feb 23, 1993

Appl. No.:

8/021693

Inventors:

Jules D. Campbell - Austin TX
Kelvin E. McCollough - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 5159
H03K 1756

US Classification:

307353

Abstract:

A sampling circuit (10, 10') selectively samples, stores and provides multiple output signals with a single amplifier (30). A sampling capacitor (20, 28) is used for each input channel. In order to minimize crosstalk between the multiple channels, each sampling capacitor is selectively electrically isolated from an input of the single amplifier by a switch (18, 25). Each sampling capacitor is further selectively electrically isolated from an output of the single amplifier by another switch (19, 26). A switch structure (50, 52, 54) which is guard ring protected may be used at the input of each channel to further minimize crosstalk errors.

US Patent:

59037482, May 11, 1999

Filed:

Aug 18, 1997

Appl. No.:

8/916733

Inventors:

Kelvin E. McCollough - Austin TX
Javier Saldana - Austin TX
Pamela Daniel - Austin TX

Assignee:

Motorola Inc. - Austin TX

International Classification:

G06F1/04

US Classification:

395558

Abstract:

Under software control, a loss of clock detect circuit (24) can be enabled to detect loss of clock. A plurality of different clock signals, including the input reference clock (34) to the PLL (12) and the feedback (36) from the PLL (12), are monitored by the loss of clock circuit (24). When the currently selected system clock (38) signal is lost, a control circuit (28) can select an optimal back-up clocking mode based on which clock signals were lost. One such selectable mode is to utilize the input reference clock (34) directly instead of the PLL (12). Another such selectable mode is to utilize the PLL (12) in a self-clocked mode to provide the system clock (38).

US Patent:

59630680, Oct 5, 1999

Filed:

Jul 28, 1997

Appl. No.:

8/901645

Inventors:

Jeffrey R. Hardesty - Austin TX
Geoffrey Hall - Austin TX
Kelvin McCollough - Austin TX

Assignee:

Motorola Inc. - Austin TX

International Classification:

H03K 104

US Classification:

327156

Abstract:

A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.

US Patent:

62158341, Apr 10, 2001

Filed:

Aug 4, 1997

Appl. No.:

8/905336

Inventors:

Kelvin McCollough - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03D 324

US Classification:

375375

Abstract:

A dual bandwidth PLL based clock generation circuit that enables device execution after frequency/phase lock has been safely achieved is provided. A PLL (410) generates a PLL clock output to a divider (430), which divides the PLL clock at a system clock output. A frequency detector (415) detects frequency/phase lock of the PLL and outputs a bandwidth control signal to selectively operate the PLL (410) in a wide or narrow bandwidth mode until the system clock is stabilized to within a predefined bandwidth of a target frequency while the PLL (410) is operating in the narrow bandwidth mode. The frequency detector (415) outputs a frequency lock signal that enables execution in a CPU (440) upon detecting that the PLL (410) has safely locked to a desired output frequency. Thus, the present invention provides a stable system clock for the system prior to the CPU (440) being allowed to begin its operation, thereby substantially avoiding system failures that may result from frequency overshoot of the system clock.