Kelly Dee Horton

US Patent:

58420410, Nov 24, 1998

Filed:

May 20, 1994

Appl. No.:

8/246673

Inventors:

Gerard T. McKee - Austin TX
Victor F. Andrade - Austin TX
Kelly McCord Horton - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300
G06F 1314

US Classification:

395843

Abstract:

An integrated processor is provided that employs an improved address decoding method during bus cycles of an external master. An external PCI master may initiate a cycle (either memory or I/O) on the PCI bus by asserting an address signal on the PCI bus along with the FRAME signal which indicates the start of the PCI cycle. After the address becomes stable, the bus interface unit transfers the address signal to the CPU local bus. The bus interface unit does not assert or drive the address strobe signal ADS at this time, however, and thus a CPU local bus cycle is not initiated. The decode logic within the memory or I/O control unit responsively decodes the address signal to determine whether the address is mapped within the address space of the respective control unit. If the address is not within the mapped space of the respective control unit, the control unit does not assert the hit signal, and thus the bus interface unit does not initiate a corresponding CPU local bus cycle and does not drive the PCI device select signal DEVSEL. The PCI bus cycle may then proceed normally in that either another PCI slave may assert the device select DEVSEL signal to indicate that it is responding to the cycle, or the cycle will be aborted by the PCI master.

US Patent:

56491611, Jul 15, 1997

Filed:

Sep 26, 1996

Appl. No.:

8/721211

Inventors:

Victor F. Andrade - Austin TX
Kelly M. Horton - Austin TX

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

395494

Abstract:

A system is disclosed for optimizing data transfer times between an external Master device and main memory. The system includes an integrated processor with a PCI bridge for orchestrating data transfers with the PCI Master over the PCI bus, and a memory controller for controlling access to the main memory. During burst cycles of the PCI Master, the PCI bridge expedites data transfers by providing the memory address to the memory controller early during periods when the PCI Master is slow in transmitting or receiving data. When the PCI Master is unable to respond in a timely fashion, and while the PCI bridge is in control of the local bus, the PCI bridge asserts a MEMWAIT signal to the memory controller to indicate the need to throttle down a data transfer. At substantially the same time, the PCI bridge supplies the memory controller with the next memory address to enable the memory controller to open the appropriate page (and/or precharge the last page) in the memory to expedite subsequent data transfers by asserting (and/or deactivating) the proper row address strobe (RAS) lines. When MEMWAIT is deasserted by the PCI bridge, the memory controller immediately responds by asserting the column address strobe to drive in or drive out the data.

US Patent:

6163848, Dec 19, 2000

Filed:

Sep 22, 1993

Appl. No.:

8/125406

Inventors:

Douglas D. Gephardt - Austin TX
Kelly M. Horton - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

713322

Abstract:

A system and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus are provided that accommodate a power conservation technique in which a peripheral bus clock signal may be stopped. If an alternate bus master requires mastership of the peripheral bus when the peripheral bus clock signal is stopped, the alternate bus master asserts a clock request signal for re-starting the peripheral bus clock. The clock request signal is broadcasted on the peripheral bus and is accordingly received by a clock control circuit. The clock control circuit responsively causes the re-starting of the peripheral bus clock signal. Subsequently, the alternate bus master can generate a bus request signal that is synchronous to the peripheral bus clock signal to thereby obtain a grant signal from a bus arbiter unit. As a result, the peripheral bus clock signal can be stopped for power management while still accommodating alternate bus masters that must assert a synchronous bus request signal to obtain mastership of the peripheral bus.