Keith T Kwietniak

US Patent:

6921978, Jul 26, 2005

Filed:

May 8, 2003

Appl. No.:

10/249799

Inventors:

Lawrence A. Clevenger - LaGrangeville NY, US
Stephen E. Greco - LaGrangeville NY, US
Keith T. Kwietniak - Highland Falls NY, US
Chih-Chao Yang - Beacon NY, US
Yun-Yu Wang - Poughquag NY, US
Kwong H. Wong - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L023/48

US Classification:

257759, 257751, 257774

Abstract:

The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

US Patent:

7060624, Jun 13, 2006

Filed:

Aug 13, 2003

Appl. No.:

10/639989

Inventors:

Panayotis Andricacos - Croton on Hudson NY, US
Emanuel Israel Cooper - Scarsdale NY, US
Timothy Joseph Dalton - Ridgefield CT, US
Hariklia Deligianni - Tenafly NJ, US
Daniel Guidotti - Atlanta GA, US
Keith Thomas Kwietniak - Highland Falls NY, US
Michelle Leigh Steen - Danbury CT, US
Cornelia Kang-I Tsang - Mohegan Lake NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/311

US Classification:

438700, 438704

Abstract:

Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.

US Patent:

7101784, Sep 5, 2006

Filed:

May 10, 2005

Appl. No.:

11/125549

Inventors:

Lawrence A. Clevenger - LaGrangeville NY, US
Stephen E. Greco - LaGrangeville NY, US
Keith T. Kwietniak - Highland Falls NY, US
Chih-Chao Yang - Beacon NY, US
Yun-Yu Wang - Poughquag NY, US
Kwong H. Wong - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438623, 438625, 438637

Abstract:

The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

US Patent:

7479213, Jan 20, 2009

Filed:

Dec 23, 2004

Appl. No.:

11/020068

Inventors:

Mizuki Nagai - Tokyo, JP
Hiroyuki Kanda - Tokyo, JP
Keiichi Kurashina - Tokyo, JP
Satoru Yamamoto - Tokyo, JP
Hidenao Suzuki - Tokyo, JP
Koji Mishima - Tokyo, JP
Hariklia Deligianni - Tenafly NJ, US
Keith Kwietniak - Highland Falls NY, US

Assignee:

Ebara Corporation - Tokyo

International Classification:

C25D 5/10

US Classification:

205170, 205157, 205171, 205173, 205174, 205182

Abstract:

A plating method is capable of preferentially precipitating a plated film fully and uniformly in trenches and via holes according to a mechanical and electrochemical process, and of easily forming a plated film having higher flatness surface without being affected by variations in the shape of trenches and via holes. The plating method includes a first plating process and a second plating process. The second plating process is performed by filling a plating solution between an anode and a substrate, with a porous member placed in the plating solution, repeatedly bringing the porous member and the substrate into and out of contact with each other, passing a current between the anode and the substrate while the porous member is being held in contact with the substrate.

US Patent:

7553400, Jun 30, 2009

Filed:

Dec 21, 2004

Appl. No.:

11/016924

Inventors:

Mizuki Nagai - Tokyo, JP
Hiroyuki Kanda - Tokyo, JP
Keiichi Kurashina - Tokyo, JP
Satoru Yamamoto - Tokyo, JP
Ryoichi Kimizuka - Kanagawa-ken, JP
Hariklia Deligianni - Yorktown Heights NY, US
Brett Baker - Yorktown Heights NY, US
Keith Kwietniak - Yorktown Heights NY, US
Panayotis Andricacos - Yorktown Heights NY, US
Phillipe Vereecken - Yorktown Heights NY, US

Assignee:

Ebara Corporation - Tokyo
International Business Machines Corporation (IBM) - Armonk NY

International Classification:

C25D 5/22

US Classification:

205 93, 205137

Abstract:

A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.

US Patent:

7863189, Jan 4, 2011

Filed:

Jan 5, 2007

Appl. No.:

11/620423

Inventors:

John Michael Cotte - New Fairfield CT, US
Hariklia Deligianni - Tenafly NJ, US
John Ulrich Knickerbocker - Monroe NY, US
Keith T. Kwietniak - Highland Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438667, 438639, 257621, 257E21585

Abstract:

Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with low defect density. In particular, methods are provided which enable fabrication of silicon carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.

US Patent:

20020027082, Mar 7, 2002

Filed:

Oct 23, 2001

Appl. No.:

09/983235

Inventors:

Panayotis Andricacos - Croton-on-Hudson NY, US
W. Horkans - Ossining NY, US
Keith Kwietniak - Highland Falls NY, US
Peter Locke - Hopewell Junction NY, US
Cyprian Uzoh - Milpitas CA, US

International Classification:

C25D021/06
C25D021/16
C25D005/02
H01L021/288
H01L021/445
C25D007/12
C25D011/32

US Classification:

205/157000, 205/098000, 205/123000

Abstract:

A method of reducing etching of a seed layer by a plating solution. Prior to introducing the semiconductor wafer with the seed layer into the plating solution, the etching power of the plating solution is diminished.

US Patent:

20040077140, Apr 22, 2004

Filed:

Oct 16, 2002

Appl. No.:

10/270486

Inventors:

Panayotis Andricacos - Croton-on-Hudson NY, US
Roy Carruthers - Stormville NY, US
Stephan Cohen - Wappingers Falls NY, US
John Cotte - New Fairfield CT, US
Lynne Gignac - Beacon NY, US
Kenneth Stein - Sandy Hook CT, US
Keith Kwietniak - Highland Falls NY, US
Seshadri Subbanna - Brewster NY, US
Horatio Wildman - Wappingers Falls NY, US
David Seeger - Congers NY, US
Andrew Simon - Fishkill NY, US

International Classification:

C25D005/00
H01L021/8238
H01L021/31
H01L021/469

US Classification:

438/240000, 438/785000, 438/782000, 205/080000

Abstract:

A uniformly thick oxide film on a substrate is formed by using an anodization apparatus which deposits a blanket precursor film on a surface of a substrate; provides electrical contact to the precursor film; moves the precursor film into contact with an electrolyte solution such that substantially all electrically conductive surfaces, e.g., pin contacts, the substrate edge and a backside of the substrate are electrically isolated from the electrolyte; ensures that the surface of the precursor film on the substrate is in direct contact with the electrolyte solution; and which applies an anodizing current and/or voltage between the precursor film and a counter electrode so as to compensate for a voltage drop resulting from the presence of the electrolyte.