Karthik Sankaranarayanan

US Patent:

20130006550, Jan 3, 2013

Filed:

Jul 1, 2011

Appl. No.:

13/175269

Inventors:

Jessica Gullbrand - Forest Grove OR, US
Willem M. Beltman - West Linn OR, US
Karthik Sankaranarayanan - Hillsboro OR, US
Jose A. Cordova - Tlaquepaque, MX
Carlos A. Lopez - Guadalajara, MX
Eric Baugh - Portland OR, US

International Classification:

G06F 19/00
G01H 1/00

US Classification:

702 56, 73645

Abstract:

Systems and methods of identifying electrical sources of audible acoustic noise may involve identifying first frequency content of a circuit board, wherein the first frequency content is associated with at least one of acoustic noise and a vibration of the circuit board. Second frequency content of an electrical signal associated with the circuit board may also be identified. In addition, a coherence between the first frequency content and the second frequency content may be determined.

US Patent:

20180246762, Aug 30, 2018

Filed:

Feb 28, 2017

Appl. No.:

15/444390

Inventors:

- Santa Clara CA, US
Gautham N. Chinya - Portland OR, US
Gokce Keskin - Sunnyvale CA, US
Hong Wang - Santa Clara CA, US
Karthik Sankaranarayanan - Tigard OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/50

Abstract:

In one embodiment, a processor comprises a processor optimization unit. The processor optimization unit is to collect runtime information associated with a computing device, wherein the runtime information comprises information indicating a performance of the computing device during program execution. The processor optimization unit is further to receive runtime optimization information for the computing device, wherein the runtime optimization information comprises information associated with one or more runtime optimizations for the computing device, and wherein the runtime optimization information is determined based on an analysis of the collected runtime information. The processor optimization unit is further to perform the one or more runtime optimizations for the computing device based on the runtime optimization information.

US Patent:

20160006350, Jan 7, 2016

Filed:

Jul 7, 2014

Appl. No.:

14/325310

Inventors:

- Santa Clara CA, US
JESSICA GULLBRAND - Forest Grove OR, US
KRISHNAN RAVICHANDRAN - Saratoga CA, US
WILLEM M. BELTMAN - West Linn OR, US
KARTHIK SANKARANARAYANAN - Cumberland RI, US
SHELDON WENG - Lake Oswego OR, US
WAYNE L. PROEFROCK - Hillsboro OR, US
HARISH K. KRISHNAMURTHY - Hillsboro OR, US
PAVAN KUMAR - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02M 3/158
H02M 3/00

Abstract:

Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.