Karl E Edwards

US Patent:

6498466, Dec 24, 2002

Filed:

May 23, 2000

Appl. No.:

09/576517

Inventors:

Karl Edwards - San Jose CA

Assignee:

Linear Technology Corp. - Milpitas CA

International Classification:

G05F 140

US Classification:

323282, 363 2117

Abstract:

A current-mode switching regulator that maintains a substantially constant maximum current limit over a virtually full range of duty cycles is provided. The regulator has a control circuit that includes a buffer circuit, an adjustable voltage clamp circuit, and a slope compensation circuit. The buffer circuit isolates a control signal from capacitive loading associated with control circuit. The threshold level of the adjustable voltage clamp circuit varies with respect to the amount of slope compensation provided to the voltage regulator. This allows a control voltage to increase as slope compensation increases so that a substantially constant maximum current limit is maintained.

US Patent:

6531909, Mar 11, 2003

Filed:

Sep 15, 1999

Appl. No.:

09/397629

Inventors:

Karl Edwards - San Jose CA

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03K 1704

US Classification:

327374, 327376, 327377

Abstract:

Techniques and circuits for high speed switching of transistors are provided. These techniques and circuits switch an output device while varying the drive current to the output device in proportion to the output current through the output device. In addition, these techniques and circuits provide a switching circuit with substantially no quiescent currents. This is accomplished by sampling the output current conducted by the output device and using the sample as a signal to drive either the output device fully ON or to switch the output device fully OFF.

US Patent:

6535042, Mar 18, 2003

Filed:

Feb 22, 2000

Appl. No.:

09/510181

Inventors:

Karl Edwards - San Jose CA

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03K 3286

US Classification:

327217, 327219, 327222

Abstract:

A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

US Patent:

6611131, Aug 26, 2003

Filed:

Sep 30, 2002

Appl. No.:

10/261916

Inventors:

Karl Edwards - San Jose CA

Assignee:

Linear Technology Corp. - Milpitas CA

International Classification:

G05F 140

US Classification:

323282, 363 2117

Abstract:

A current-mode switching regulator that maintains a substantially constant maximum current limit over a virtually full range of duty cycles is provided. The regulator has a control circuit that includes a buffer circuit, an adjustable voltage clamp circuit, and a slope compensation circuit. The buffer circuit isolates a control signal from capacitive loading associated with control circuit. The threshold level of the adjustable voltage clamp circuit varies with respect to the amount of slope compensation provided to the voltage regulator. This allows a control voltage to increase as slope compensation increases so that a substantially constant maximum current limit is maintained.

US Patent:

6750690, Jun 15, 2004

Filed:

Jan 22, 2003

Appl. No.:

10/350927

Inventors:

Karl Edwards - San Jose CA

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03K 312

US Classification:

327217, 327199, 327200

Abstract:

A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

US Patent:

6847245, Jan 25, 2005

Filed:

Jan 22, 2003

Appl. No.:

10/350670

Inventors:

Karl Edwards - San Jose CA, US

Assignee:

Linear Technology Corp. - Milpitas CA

International Classification:

H03K 312

US Classification:

327217, 327215, 327219

Abstract:

A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

US Patent:

6861892, Mar 1, 2005

Filed:

Jan 22, 2003

Appl. No.:

10/350552

Inventors:

Karl Edwards - San Jose CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03K017/04

US Classification:

327374, 327376, 327377

Abstract:

Techniques and circuits for high speed switching of transistors are provided. These techniques and circuits switch an output device while varying the drive current to the output device in proportion to the output current through the output device. In addition, these techniques and circuits provide a switching circuit with substantially no quiescent currents. This is accomplished by sampling the output current conducted by the output device and using the sample as a signal to drive either the output device fully ON or to switch the output device fully OFF.

US Patent:

7173465, Feb 6, 2007

Filed:

Mar 10, 2005

Appl. No.:

11/077297

Inventors:

Karl Edwards - San Jose CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03K 3/037

US Classification:

327217, 327199, 327200, 327201, 327204, 327207

Abstract:

A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.