Kamran Malik

US Patent:

6389527, May 14, 2002

Filed:

Feb 8, 1999

Appl. No.:

09/246406

Inventors:

Michael Raam - Cupertino CA
Toru Utsumi - Kawasaki, JP
Takeki Osanai - Ebina, JP
Kamran Malik - San Jose CA

Assignee:

Kabushiki Kaisha Toshiba

International Classification:

G06F 1500

US Classification:

712 38, 712 32, 711122, 711131, 711136, 711138, 711139, 711141, 711145, 711146

Abstract:

The present invention comprises a LSU which executes instructions relating to load/store. The LSU includes a DCACHE which temporarily stores data read from and written to the external memory, an SPRAM used to specific purposes other than cache, and an address generator generating virtual addresses for access to the DCACHE and the SPRAM. Because the SPRAM can load and store data by a pipeline of the LSU and exchanges data with an external memory through a DMA transfer, the present invention is especially available to high-speedily process a large amount of data such as the image data. Because the LSU can access the SPRAM with the same latency as that of the DCACHE, after data being stored in the external memory is transferred to the SPRAM, the processor can access the SPRAM in order to perform data process, and it is possible to process a large amount of data with shorter time than time necessary to directly access an external memory.

US Patent:

6412057, Jun 25, 2002

Filed:

Feb 8, 1999

Appl. No.:

09/246407

Inventors:

Masashi Sasahara - Kawasaki, JP
Rakesh Agarwal - Palo Alto CA
Kamran Malik - San Jose CA
Michael Raam - Cupertino CA

Assignee:

Kabushiki Kaisha Toshiba - Kawasaki

International Classification:

G06F 1200

US Classification:

711202

Abstract:

A microprocessor includes an MMU which converts from a virtual address to a physical address, and an LSU which controls an execution of a load/store instruction. The LSU includes a DCACHE which temporarily stores data to read out from and to write into an external memory, an SPRAM used for a specific purpose besides caching, and an address generator which generates the virtual address to access the DCACHE and the SPRAM. The MMU generates a conversion table which performs a conversion from the virtual address to the physical address. A flag information showing whether or not the access to the SPRAM is performed is included in this conversion table. The LSU absolutely accesses the SPRAM if the flag is being set. Accordingly, it is unnecessary to allocate the SPRAM to a memory map of the main memory, and the allocation of the memory map simplifies.

US Patent:

7042891, May 9, 2006

Filed:

Jan 4, 2001

Appl. No.:

09/755670

Inventors:

Stuart F. Oberman - Sunnyvale CA, US
Anil Mehta - Milpitas CA, US
Rodney N. Mullendore - San Jose CA, US
Kamran Malik - San Jose CA, US

Assignee:

Nishan Systems, Inc. - Broomfield CO

International Classification:

H04L 12/56
H04L 12/26

US Classification:

370412, 370428, 370230

Abstract:

A system and method for low latency switching of data packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Under normal operation, the data transport logic stores packet data into the memory. Later, the packet data is read from the memory and output to a destination output port. To reduce latency when the switch is not congested, the switching logic may be configured to perform a cut-through operation by routing packets directly from input ports to output ports without storing any portion of the packet in the memory. Alternatively, the switch may begin forwarding the stored packet data to the output port before the entire packet has been received or stored in the memory.

US Patent:

7215680, May 8, 2007

Filed:

May 13, 2002

Appl. No.:

10/144187

Inventors:

Rodney N. Mullendore - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US
Anil Mehta - Milpitas CA, US
Keith Schakel - San Jose CA, US
Kamran Malik - San Jose CA, US

Assignee:

Nishan Systems, Inc. - San Jose CA

International Classification:

H04L 12/56

US Classification:

370412

Abstract:

A system and method for enabling a network switch to transmit queued packets to a device when opened by the device, and thus to utilize the Fibre Channel Arbitrated Loop (FC-AL) in full-duplex mode when possible. The switch may include a plurality of queues each associated with a device on the FC-AL for queuing incoming packets for the device. The switch may determine a next non-empty queue, open the device associated with the queue, and send packets to the device. The device may send packets to the switch concurrently with receiving packets from the switch, thus utilizing the FC-AL in full-duplex mode. When a device opens the switch to transmit packets to the switch, the switch may determine if there are packets for the device in the queue and, if so, send packets to the device concurrently with receiving packets from the device, thus utilizing the FC-AL in full-duplex mode.

US Patent:

7227841, Jun 5, 2007

Filed:

May 13, 2002

Appl. No.:

10/144081

Inventors:

Rodney N. Mullendore - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US
Anil Mehta - Milpitas CA, US
Keith Schakel - San Jose CA, US
Kamran Malik - San Jose CA, US

Assignee:

Nishan Systems, Inc. - Broomfield CO

International Classification:

G01R 31/08

US Classification:

370230

Abstract:

A system and method for input thresholding packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the network switch may be assigned to one of a plurality of threshold groups and to one of a plurality of flows within the threshold group. In one embodiment, each threshold group may be divided into a plurality of levels of operation. As resources are allocated or freed by the threshold group, the threshold group may dynamically move up or down in the levels of operation. Within each level, one or more different values may be used as level boundaries and resource limits for flows within the threshold group. In one embodiment, programmable registers may be used to store these values.

US Patent:

7283556, Oct 16, 2007

Filed:

Jul 31, 2002

Appl. No.:

10/209158

Inventors:

Rodney N. Mullendore - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US
Anil Mehta - Milpitas CA, US
Keith Schakel - San Jose CA, US
Kamran Malik - San Jose CA, US

Assignee:

Nishan Systems, Inc. - Broomfield CO

International Classification:

H04L 12/43

US Classification:

370458, 370442

Abstract:

A system and method for managing the allocation of Time Division Multiplexing (TDM) timeslots in a network switch. The network switch may use a TDM cycle comprising multiple timeslots to manage shared resources and to schedule data ingress and egress through the ports of the current configuration, wherein each port is assigned one or more timeslots. The network switch may be reprogrammed to support one of multiple timeslot assignment schemes for one of multiple port configurations. The network switch may support configurations with varying numbers of ports, e. g. 8- and 16-port configurations. A network switch may also support configurations where two or more ports are combined to form one port, for example, a 2 Gbs Fibre Channel port. To meet the requirements of the various configurations, the timeslot assignment scheme may be reprogrammed to meet the scheduling requirements of each of the possible port configurations.

US Patent:

7406041, Jul 29, 2008

Filed:

Jul 31, 2002

Appl. No.:

10/209545

Inventors:

Rodney N. Mullendore - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US
Anil Mehta - Milpitas CA, US
Keith Schakel - San Jose CA, US
Kamran Malik - San Jose CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

H04L 12/26

US Classification:

370230, 370411, 370429

Abstract:

A system and method for late-dropping packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Packets entering the switch may be subject to input thresholding, and may be assigned to a flow within a group. A portion of a packet subject to input thresholding may be accepted into the switch and assigned to a group and flow even if, at the time of arrival of the portion, there are not enough resources available to receive the remainder of the packet. This partial receipt of the packet is allowed because of the possibility of additional resources becoming available between the time of receipt of and resource allocation for the portion of the packet and receipt of subsequent portions of the packet.

US Patent:

7809852, Oct 5, 2010

Filed:

May 22, 2002

Appl. No.:

10/152763

Inventors:

Rodney N. Mullendore - San Jose CA, US
Stuart F. Oberman - Sunnyvale CA, US
Anil Mehta - Milpitas CA, US
Keith Schakel - San Jose CA, US
Kamran Malik - San Jose CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

G06F 13/00

US Classification:

709234

Abstract:

A system and method for converting low-jitter, interleaved frame traffic, such as that generated in an IP network, to high jitter traffic to improve the utilization of bandwidth on arbitrated loops such as Fibre Channel Arbitrated Loops. Embodiments of a high jitter scheduling algorithm may be used in devices such as network switches that interface an arbitrated loop with an IP network that carries low-jitter traffic. The high jitter algorithm may use a separate queue for each device on the arbitrated loop, or alternatively may use one queue for two or more devices. Incoming frames are distributed among the queues based upon each frame's destination device. The scheduling algorithm may then service the queues and forward queued frames to the devices from the queues. In one embodiment, the queues are serviced in a round-robin fashion. In one embodiment, each queue may be serviced for a programmed limit.