Kamran S Malik

US Patent:

6412057, Jun 25, 2002

Filed:

Feb 8, 1999

Appl. No.:

09/246407

Inventors:

Masashi Sasahara - Kawasaki, JP
Rakesh Agarwal - Palo Alto CA
Kamran Malik - San Jose CA
Michael Raam - Cupertino CA

Assignee:

Kabushiki Kaisha Toshiba - Kawasaki

International Classification:

G06F 1200

US Classification:

711202

Abstract:

A microprocessor includes an MMU which converts from a virtual address to a physical address, and an LSU which controls an execution of a load/store instruction. The LSU includes a DCACHE which temporarily stores data to read out from and to write into an external memory, an SPRAM used for a specific purpose besides caching, and an address generator which generates the virtual address to access the DCACHE and the SPRAM. The MMU generates a conversion table which performs a conversion from the virtual address to the physical address. A flag information showing whether or not the access to the SPRAM is performed is included in this conversion table. The LSU absolutely accesses the SPRAM if the flag is being set. Accordingly, it is unnecessary to allocate the SPRAM to a memory map of the main memory, and the allocation of the memory map simplifies.

US Patent:

63082527, Oct 23, 2001

Filed:

Feb 4, 1999

Appl. No.:

9/244443

Inventors:

Rakesh Agarwal - Palo Alto CA
Kamran Malik - San Jose CA
Tatsuo Teruyama - Kawasaki, JP

Assignee:

Kabushiki Kaisha Toshiba - Kawasaki

International Classification:

G06F 1580

US Classification:

712 22

Abstract:

A processor includes n-bit (e. g. , 128-bit) register circuitry for holding instruction operands. Instruction decode circuitry decodes processor instructions from an instruction stream. Arithmetic logic (AL) circuitry is operable to perform one of a single operation on at least one m-bit maximum (e. g. , 64-bit) operand provided from the n-bit register circuitry, responsive to a first single processor instruction decoded by the instruction decode circuitry, wherein m