Kalpesh Hira

US Patent:

20100017187, Jan 21, 2010

Filed:

Jul 15, 2008

Appl. No.:

12/173217

Inventors:

Kalpesh Hira - Austin TX, US
Neil A. Panchal - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

703 15

Abstract:

Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, and then dividing them into two groups based on the random order with high and low logical states respectively assigned to the two groups. In a specific implementation the latch states are set using an HDL force command prior to applying the reset signal, and the force command is removed after applying the reset signal using an HDL release command. If the circuit description is a gate-level netlist, then logical states of gates within the storage elements are also set.

US Patent:

20170177780, Jun 22, 2017

Filed:

Mar 9, 2017

Appl. No.:

15/455107

Inventors:

- Armonk NY, US
KALPESH HIRA - AUSTIN TX, US
GIANG NGUYEN - AUSTIN TX, US
BILL N. ON - AUSTIN TX, US
JAMES M. RAKES - AUSTIN TX, US

International Classification:

G06F 17/50

Abstract:

A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

US Patent:

20170116355, Apr 27, 2017

Filed:

Jan 10, 2017

Appl. No.:

15/402492

Inventors:

- Armonk NY, US
KALPESH HIRA - AUSTIN TX, US
GIANG NGUYEN - AUSTIN TX, US
BILL N. ON - AUSTIN TX, US
JAMES M. RAKES - AUSTIN TX, US

International Classification:

G06F 17/50

Abstract:

A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

US Patent:

20160364506, Dec 15, 2016

Filed:

Aug 16, 2016

Appl. No.:

15/237911

Inventors:

- ARMONK NY, US
KALPESH HIRA - AUSTIN TX, US
GIANG NGUYEN - AUSTIN TX, US
BILL N. ON - AUSTIN TX, US
JAMES M. RAKES - AUSTIN TX, US

International Classification:

G06F 17/50

Abstract:

A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

US Patent:

20150350175, Dec 3, 2015

Filed:

Jun 3, 2014

Appl. No.:

14/294219

Inventors:

- Armonk NY, US
Ronald Dwayne Martin - Round Rock TX, US
Kalpesh Hira - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 29/06
H04L 29/08

Abstract:

A network-based appliance includes a mechanism to erase data on the appliance's local storage. The appliance's normal system reset operation is overridden to enable a local user to place the appliance into a safe mode during which remote erasure of the storage is permitted, provided that mode is entered within a first time period following initiation of a system reset. If the appliance is placed in the mode within the time period, it can then receive commands to wipe the local storage. Once the safe mode is entered by detecting one or more actions of a local user, preferably the appliance data itself is wiped by another person or entity that is remote from the device. Thus, physical (local) presence to the appliance is necessary to place the device in the safe mode, while non-physical (remote) presence with respect to the appliance enables actual wiping of the storage device.

US Patent:

20150350218, Dec 3, 2015

Filed:

Sep 30, 2014

Appl. No.:

14/503121

Inventors:

- Armonk NY, US
Ronald Dwayne Martin - Round Rock TX, US
Kalpesh Hira - Austin TX, US

International Classification:

H04L 29/06
G06F 21/62

Abstract:

A network-based appliance includes a mechanism to erase data on the appliance's local storage. The appliance's normal system reset operation is overridden to enable a local user to place the appliance into a safe mode during which remote erasure of the storage is permitted, provided that mode is entered within a first time period following initiation of a system reset. If the appliance is placed in the mode within the time period, it can then receive commands to wipe the local storage. Once the safe mode is entered by detecting one or more actions of a local user, preferably the appliance data itself is wiped by another person or entity that is remote from the device. Thus, physical (local) presence to the appliance is necessary to place the device in the safe mode, while non-physical (remote) presence with respect to the appliance enables actual wiping of the storage device.