Jurgen M Schulz

US Patent:

6512704, Jan 28, 2003

Filed:

Sep 14, 2001

Appl. No.:

09/952951

Inventors:

Chung-Hsiao R. Wu - Sunnyvale CA
Jyh-Ming Jong - Saratoga CA
Lee A. Warner - Redwood City CA
Jurgen M. Schulz - Pleasanton CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G11C 1604

US Classification:

36518907, 365233, 365193, 365194

Abstract:

A data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a flip-flop. The flip-flop has a preset input that is coupled to the output of the second comparator.

US Patent:

6636074, Oct 21, 2003

Filed:

Jan 22, 2002

Appl. No.:

10/054811

Inventors:

Jurgen M. Schulz - Pleasanton CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H03K 1900

US Classification:

326 93, 326136, 327141

Abstract:

Various systems and methods for reducing the power consumption of CSRs (Control and Status Registers) within an integrated circuit (IC) are disclosed. In one embodiment, an IC includes a plurality of CSRs. Each CSR includes one or more flip-flops that are used to store one or more bits of control and/or status information for an associated device on the IC. The IC also includes one or more clock gates. Each clock gate is coupled to provide a gated clock signal to one or more of the flip-flops in a respective one of the CSRs. Each clock gate is configured to output a clock signal as the gated clock signal if a clock enable signal that corresponds to the respective CSR is asserted. The IC also includes one or more clock gating units that are each configured to generate the clock enable signal for a respective one of the CSRs.

US Patent:

6640322, Oct 28, 2003

Filed:

Mar 22, 2000

Appl. No.:

09/532383

Inventors:

Jurgen M. Schulz - Pleasanton CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G01R 3128

US Classification:

714724, 714730

Abstract:

An integrated circuit is presented having a plurality of logic modules dispersed about a surface of a semiconductor substrate. Each logic module includes a set of control and status registers including at least one control register storing a control value. A functional unit of each logic module performs one or more logic functions dependent upon the control value stored in the control register. A central controller is coupled to the each of the logic modules. The central controller is adapted to receive address, data, and control signals (e. g. , from signal lines of an external bus coupled to I/O pads of the integrated circuit), and issues read/write commands to read/write the control and status registers dependent upon the address, data, and control signals. A write command may, for example, modify the control value stored in a selected one of the control registers. The integrated circuit may include a bus which couples the central controller to each of the logic modules.

US Patent:

6668346, Dec 23, 2003

Filed:

Nov 10, 2000

Appl. No.:

09/709970

Inventors:

Jurgen M. Schulz - Pleasanton CA
Tai Quan - San Jose CA
Brian L. Smith - Sunnyvale CA
Michael J. Grubisich - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G01R 3128

US Classification:

714724, 324763, 327105

Abstract:

A digital process monitor for measuring the performance of an integrated circuit has been developed. The digital process monitor includes: a ring oscillator that generates a series of clocked pulses, and a ripple counter that counts the clocked pulses. The count is measured for a prescribed period of time and the count corresponds to the performance of the integrated circuit.

US Patent:

6674644, Jan 6, 2004

Filed:

Nov 1, 2001

Appl. No.:

10/044055

Inventors:

Jurgen Schulz - Pleasanton CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H05K 114

US Classification:

361728, 361730, 361803, 361807, 439637

Abstract:

A module and a corresponding connector that include multiple rows of contacts is described. In one embodiment, the module may include a channel formed in a bottom edge of the module. A plurality of contacts may be disposed on the inner surface of the channel and the outer surface of the module. A complementary connector is also described.

US Patent:

6681337, Jan 20, 2004

Filed:

Apr 25, 2000

Appl. No.:

09/557987

Inventors:

Brian L. Smith - Sunnyvale CA
Jurgen M. Schulz - Sunnyvale CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 700

US Classification:

713400, 711167, 703 13, 365233

Abstract:

An integrated circuit includes an address register, clocked by the clock signal corresponding to the TAP, used to address a control/status register within the integrated circuit. The address register receives a signal indicating that an address is to be loaded into the address register. A control circuit is coupled to receive the signal and to generate a second signal responsive to the address register being loaded. A shadow register, clocked by the clock signal of the integrated circuit, is coupled to receive the second signal and to load a value from the control/status register addressed by the address loaded into the address register responsive to the second signal. In this manner, a valid value from the addressed register is synchronized in the clock domain of the addressed register. The value for the shadow register may subsequently be synchronized into the clock domain of the TAP, and subsequently transferred out of the integrated circuit via the test interface.

US Patent:

6802036, Oct 5, 2004

Filed:

Nov 19, 2001

Appl. No.:

09/992351

Inventors:

Kenneth Y. Chiu - San Francisco CA
Jurgen M. Schulz - Pleasanton CA
Daniel F. McMahon - Freemont CA
Debaleena Das - Woburn MA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H04L 118

US Classification:

714751, 714 5, 710 52, 711100, 345558

Abstract:

A buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first memory having an input and an output. The input of the first memory is coupled to the first buffer input. The buffer also includes a second memory. The second memory has an input and an output. The input of the second memory is coupled to the second buffer input. The buffer also includes a first register. The first register has an input and an output. The input of the first register is coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory. The output of the first register is coupled to the buffer output. The buffer also includes a second register configured to store a second data entry.

US Patent:

6959361, Oct 25, 2005

Filed:

Apr 25, 2002

Appl. No.:

10/132643

Inventors:

Jurgen M. Schulz - Pleasanton CA, US
David C. Stratman - Mountain View CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F013/00

US Classification:

711120, 709223, 709202, 711154, 711158, 711168, 710240

Abstract:

One embodiment of the present invention provides a memory controller that contains a distributed cache that stores cache lines for pending memory operations. This memory controller includes an input that receives memory operations that are directed to an address in memory. It also includes a central scheduling unit and multiple agents that operate under control of the central scheduling unit. Upon receiving a current address, a given agent compares the current address with a cache line stored within the given agent. All of the agents compare the current address with their respective cache line in parallel. If the addresses match, the agent reports the result to the rest of the agents in the memory controller, and accesses data within the matching cache line stored within the agent to accomplish the memory operation.

Author:

Jurgen Schulz

ISBN #:

3861084953