California Micro Devices Corporation Semiconductors and Related Devices
430 N Mccarthy Blvd, Milpitas, CA 95035
Juergen Lutz Chief Information Officer, Chief Technology Officer, VP Information Services
California Micro Devices Electrical Contractor
215 Topaz St, Milpitas, CA 95035 408 934-3147
Us Patents
System And Method For Utilizing A Two-Dimensional Adaptive Filter For Reducing Flicker In Interlaced Television Images Converted From Non-Interlaced Computer Graphics Data
A system and method for conversion of graphics from computer graphics formats to television formats is disclosed. More particularly, an improved scaling and flicker reduction system and method is disclosed for scaling personal computer (PC) graphics formats into different resolution television (TV) formats and for reducing flicker due to the conversion process of interlacing non-interlaced PC graphics to match interlaced TV formats. The scaling implementation reduces line buffer requirements by using a conditional scaling technique for converting graphics from a PC resolution format to a TV resolution format. The flicker reduction implementation provides a two-dimensional adaptive filter that selects between multiple filters so that different parts of an image may have different flicker reduction and different levels of trade off between flicker reduction and resolution. The system and method disclosed are more generally applicable to converting images from one resolution to another and to reducing flicker in images converted from a non-interlaced format to an interlaced format.
Digital Carrier Synthesis Synchronized To A Reference Signal That Is Asynchronous With Respect To A Digital Sampling Clock
Ronald D. Malcolm - Austin TX Juergen M. Lutz - Austin TX
Assignee:
Cirrus Logic, Inc. - Fremont CA
International Classification:
H04N 512
US Classification:
348537
Abstract:
A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal, for example, by an up/down counter that is incremented or decremented each cycle of the reference signal and is decremented or incremented each cycle of the digital carrier signal to compute the adjustment value.
Phase Comparison And Phase Adjustment For Synchronization To A Reference Signal That Is Asynchronous With Respect To A Digital Sampling Clock
Ronald D. Malcolm - Austin TX Juergen Lutz - Austin TX
International Classification:
H04N 512 H03L 700
US Classification:
348537
Abstract:
A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal, for example, by an up/down counter that is incremented or decremented each cycle of the reference signal and is decremented or incremented each cycle of the digital carrier signal to compute the adjustment value.
System And Method For Scaling Images And Reducing Flicker In Interlaced Television Images Converted From Non-Interlaced Computer Graphics Data
A system and method for conversion of graphics from computer graphics formats to television formats is disclosed. More particularly, an improved scaling and flicker reduction system and method is disclosed for scaling personal computer (PC) graphics formats into different resolution television (TV) formats and for reducing flicker due to the conversion process of interlacing non-interlaced PC graphics to match interlaced TV formats. The scaling implementation reduces line buffer requirements by using a conditional scaling technique for converting graphics from a PC resolution format to a TV resolution format. The flicker reduction implementation provides a two-dimensional adaptive filter that selects between multiple filters so that different parts of an image may have different flicker reduction and different levels of trade off between flicker reduction and resolution. The system and method disclosed are more generally applicable to converting images from one resolution to another and to reducing flicker in images converted from a non-interlaced format to an interlaced format.
Digital Carrier Synthesis By Counting Cycles For Synchronization To A Reference Signal That Is Asynchronous With Respect To A Digital Sampling Clock
Ronald D. Malcolm - Austin TX Juergen M Lutz - Austin TX
Assignee:
Crystal Semiconductor Corp. - Fremont CA
International Classification:
H04N 512
US Classification:
348537
Abstract:
A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment value. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal, for example, by an up/down counter that is incremented or decremented each cycle of the reference signal and is decremented or incremented each cycle of the digital carrier signal to compute the adjustment value.
InVue Security Products - Charlotte, North Carolina Area since Apr 2013
VP engineering
JML consulting - Austin, Texas Area Jun 2010 - Mar 2013
Principal
Sydaap Technologies - Austin, Texas Area Oct 2011 - Mar 2012
Business Development Executive
California Micro Devices / ON Semiconductor Jul 2005 - May 2010
VP Engineering
Cirrus Logic 1994 - 2005
VP Engineering
Education:
Universität Stuttgart 1979 - 1984
MSEE, Electrical Engineering
Apr 2013 to 2000 Vice President EngineeringJML Consulting Austin, TX Jun 2010 to Mar 2013 Independent Consultant/ContractorCalifornia Micro Devices/ON Semiconductor Milpitas, CA Jul 2005 to May 2010 VP EngineeringCirrus Logic
Jan 2005 to Jun 2005 VP of IC Engineering Embedded ProductsCirrus Logic Austin, TX Feb 1994 to Jun 2005 VP engineeringCirrus Logic
May 2002 to Dec 2004 VP of Integrated Circuit EngineeringCirrus Logic
Jun 2001 to May 2002 Director of Strategic Business DevelopmentCirrus Logic
Mar 1999 to May 2001 Director of EngineeringCirrus Logic
Feb 1998 to Mar 1999 Director of EngineeringCirrus Logic
Feb 1994 to 1998 Design ManagerLSI Logic Corporation
Oct 1991 to Feb 1994 Design Engineering ManagerLSI Logic Corporation
Mar 1991 to Sep 1991 Staff EngineerITT Semiconductors/Micronas, Freiburg, Germany
Sep 1988 to Feb 1991 Engineering ManagerITT Semiconductors/Micronas, Freiburg, Germany
May 1986 to Aug 1988 Design EngineerAT&T Bell Laboratories Holmdel, NJ Jun 1985 to May 1986 Member of Technical Staff
Education:
University of Stuttgart Stuttgart 1985 MSEE
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