Judy J Johnson

US Patent:

20040078653, Apr 22, 2004

Filed:

Oct 21, 2002

Appl. No.:

10/277201

Inventors:

Kenneth Chan - Hopewell Junction NY, US
Henry Chin - Pittsburgh PA, US
Judy Johnson - Poughkeepsie NY, US
Kevin Kark - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F011/00

US Classification:

714/013000

Abstract:

A computer system enabling dynamic sparing employs a standby component which is identical to three other additional components and which operates like these other three active components while the computer system is running. Any one of these three other active components can be spared out dynamically in the computer system while it is running using a result of voting scheme and connecting of these four components in such a way that the system can dynamically spare while the system is still in operation. Such dynamic sparing gives the system a better reliability and availability when compared to today's computer system.

US Patent:

20050240801, Oct 27, 2005

Filed:

Apr 6, 2004

Appl. No.:

10/818569

Inventors:

Judy Johnson - Poughkeepsie NY, US
Kevin Kark - Poughkeepsie NY, US
George Wellwood - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F011/00

US Classification:

714005000

Abstract:

Memory is scrubbed by an improved non-linear method giving scrubbing preference to the central storage region having the characteristic of a high risk read-only memory such as the CPA region to prevent the accumulation of temporary data errors. The chip row on which the CPA resides is scrubbed after each time the scrubbing of a non-CPA chip row in a PMA completed successfully. The next non-CPA least recently scrubbed chip row would be selected for scrubbing after scrubbing completed on the CPA chip row. This in a first case provides non-linear selection methods of scrubbing central storage of computer systems to more frequently select (“select” herein encompasses the meaning of “favor”) scrub regions having the characteristic of a predominately read-only memory making those regions at a higher risk of failure than those regions having lower risk because of frequent write operations. In a second case, scrub regions having the characteristic of a predominately read-only memory are selected by using a second preferred embodiment selection method which uses the detection of faulty data from normal system accesses to central storage to identify other high risk regions and scrub them before other lower risk regions. In addition, the severity of the detected data error can be used to determine the rate at which scrub commands are sent to the selected region: the higher the severity, the higher the scrub rate.

US Patent:

20120173936, Jul 5, 2012

Filed:

Dec 29, 2010

Appl. No.:

12/981017

Inventors:

Judy S. Johnson - Poughkeepsie NY, US
Patrick J. Meaney - Poughkeepsie NY, US
Eldee Stephens - Waterbury CT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 11/10

US Classification:

714718, 714E11052

Abstract:

Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.

US Patent:

20130191685, Jul 25, 2013

Filed:

Jan 19, 2012

Appl. No.:

13/353814

Inventors:

Eldee Stephens - Waterbury CT, US
Patrick J. Meaney - Poughkeepsie NY, US
Judy S. Johnson - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H03M 13/05
G06F 11/10

US Classification:

714 15, 714E11034

Abstract:

Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel.

US Patent:

20130191698, Jul 25, 2013

Filed:

Jan 19, 2012

Appl. No.:

13/353925

Inventors:

Patrick J. Meaney - Poughkeepsie NY, US
Eldee Stephens - Waterbury CT, US
Judy S. Johnson - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS CORPORATION - Armonk NY

International Classification:

H03M 13/00

US Classification:

714758, 714763

Abstract:

Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic.

US Patent:

20130191703, Jul 25, 2013

Filed:

Jan 19, 2012

Appl. No.:

13/353879

Inventors:

Patrick J. Meaney - Poughkeepsie NY, US
William J. Clarke - Poughkeepsie NY, US
Eldee Stephens - Waterbury CT, US
Judy S. Johnson - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H03M 13/05
G06F 11/10

US Classification:

714770, 714763, 714E11034

Abstract:

Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.

US Patent:

20140101481, Apr 10, 2014

Filed:

Dec 11, 2013

Appl. No.:

14/102568

Inventors:

- Armonk NY, US
Patrick J. Meaney - Poughkeepsie NY, US
Judy S. Johnson - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS CORPORATION - Armonk NY

International Classification:

G06F 11/08

US Classification:

714 15

Abstract:

Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel.

US Patent:

20140101518, Apr 10, 2014

Filed:

Dec 11, 2013

Appl. No.:

14/102579

Inventors:

- Armonk NY, US
William J. Clarke - Poughkeepsie NY, US
Eldee Stephens - Waterbury CT, US
Judy S. Johnson - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/10

US Classification:

714770, 714763

Abstract:

Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.

Author:

Judy A. Johnson

ISBN #:

1933572027

Author:

Judy Johnson

ISBN #:

1740762053

Author:

Judy Johnson

ISBN #:

0486264327

Author:

Judy Johnson

ISBN #:

0486264572

Author:

Judy Johnson

ISBN #:

0486266222

Author:

Judy Johnson

ISBN #:

0486266230

Author:

Judy Johnson

ISBN #:

0486268438

Author:

Judy Johnson

ISBN #:

0486279243