Joyce C Sum

US Patent:

60279958, Feb 22, 2000

Filed:

Aug 18, 1998

Appl. No.:

9/135618

Inventors:

Chien Chiang - Fremont CA
Chuanbin Pan - Santa Clara CA
Vicky M. Ochoa - Pleasanton CA
Sychyi Fang - Palo Alto CA
David B. Fraser - Danville CA
Joyce C. Sum - Cupertino CA
Gary William Ray - Mountain View CA
Jeremy A. Theil - Menlo Park CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2128

US Classification:

438623

Abstract:

An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.

US Patent:

58864105, Mar 23, 1999

Filed:

Jun 26, 1996

Appl. No.:

8/670624

Inventors:

Chien Chiang - Fremont CA
Chuanbin Pan - Santa Clara CA
Vicky M. Ochoa - Pleasanton CA
Sychyi Fang - Palo Alto CA
David B. Fraser - Danville CA
Joyce C. Sum - Cupertino CA
Gary William Ray - Mountain View CA
Jeremy A. Theil - Menlo Park CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23485

US Classification:

257759

Abstract:

An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.