Joseph A Skupnjak

US Patent:

47854235, Nov 15, 1988

Filed:

Jan 22, 1987

Appl. No.:

7/005927

Inventors:

Joseph A. Skupnjak - Folsom CA
Abid Asghar - Davis CA
Kirby S. Hallenbeck - Shingle Springs CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700
G11C 1134

US Classification:

365189

Abstract:

An improved architecture for an EPROM PAL utilizing two bit lines is disclosed. The drains of the EPROM cells of a given column of an array are coupled together to a first bit line. The first line is coupled to a sensing circuit. The sources of the EPROM cells are coupled together to a second bit line which is then coupled through a current limiting transistor. The gate of the transistor is coupled to the first bit line to receive a feedback signal for controlling the current on the bit lines. The current limiting feature provides for shorter transition periods between "on" and "off" states which results in an improved speed performance of the device.

Address:

754 Glen-Mady Way, Folsom, CA 95630

VIN:

5NPEU46F08H399875

Make:

HYUNDAI

Model:

SONATA

Year:

2008